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參數(shù)資料
| 型號： | LVT22V10-DN |
| 英文描述： | Fuse-Programmable PLD |
| 中文描述： | 保險絲，可編程的PLD |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 185K |
| 代理商： | LVT22V10-DN |
Philips Semiconductors
Product specification
LVT22V10
3V high speed, universal PLD device
1998 Feb 10
8
Output Register Preload
The register on the LVT22V10 can be preloaded from the output
pins to facilitate functional testing of complex state machine designs.
This feature allows direct loading of arbitrary states, making it
unnecessary to cycle through long test vector sequences to reach a
desired state. In addition, transitions from illegal states can be
verified by loading illegal states and observing proper recovery. The
procedure for preloading follows:
1. Raise V
CC
to 3.3V
±
0.3V.
2. Set pin 2 or 3 to V
HH
to disable outputs and enable preload.
3. Apply the desired value (V
ILP
/V
IHP
) to all registered output pins.
Leave combinatorial output pins floating.
4. Clock Pin 1 from V
ILP
to V
IHP
.
5. Remove V
ILP
/V
IHP
from all registered output pins.
6. Lower pin 2 or 3 to V
ILP
.
7. Enable the output registers according to the programmed
pattern.
8. Verify V
OL
/V
OH
at all registered output pins. Note that the output
pin signal will depend on the output polarity.
PRELOAD SET-UP
LIMITS
SYMBOL
PARAMETER
MIN
REC
MAX
UNIT
V
HH
Super-level input voltage
9.5
9.5
10
V
V
ILP
Low-level input voltage
0
0
0.8
V
V
IHP
High-level input voltage
2.4
3.3
3.6
V
t
D
Delay time
100
200
1000
ns
t
I/O
I/O valid after Pin 2 or 3 drops from V
HH
to V
ILP
100
ns
t
D
V
HH
V
IHP
V
OH
V
OL
V
ILP
V
IHP
V
ILP
t
I/O
PINS 2, 3
REGISTERED
OUTPUTS
CLOCK
t
D
t
D
t
D
t
D
Output Register Preload Waveform
DATA IN
DATA OUT
V
ILP
SP00373
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