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參數(shù)資料
| 型號(hào)： | LVT22V10-BN |
| 英文描述： | Fuse-Programmable PLD |
| 中文描述： | 保險(xiǎn)絲，可編程的PLD |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 185K |
| 代理商： | LVT22V10-BN |
Philips Semiconductors
Product specification
LVT22V10
3V high speed, universal PLD device
1998 Feb 10
7
PRODUCT FEATURES
Low Ground Bounce
The Philips Semiconductors BiCMOS QUBiC process results in
exceptional noise immunity. Ground bounce is noise that is
generated on a non-switching active low output when other outputs
on the device switch from high to low. The worst case condition
occurs when 9 outputs simultaneously switch from high to low and
the tenth output is active low. The ground bounce on this tenth
output for Philips LVT22V10 is typically less than 0.7V.
V
CC
Bounce
V
CC
bounce occurs on a non-switching active high output when
other outputs are making a low to high transition. This specification
is important to consider in 3.3V designs because of the reduced
noise margin between V
CC
and V
OH
of only 1.3V relative to the
traditional 5V system’s noise margin of 3V. The Philips LVT22V10
V
CC
bounce of an output held high while the remaining 9 outputs
switch from low to high is typically less than 1.0V in magnitude.
Live Insertion/Extraction Capability
There are some inherent problems associated with inserting or
extracting an unpowered module from a powered-up, active system.
The LVT22V10 outputs have been designed such that any chance of
bus contention, glitching or clamping is eliminated.
Detailed information on this feature is provided in an application note
AN051: Philips PLDs Support Live Insertion Applications
Bus Hold Input Structure
Bus Hold is a feature that maintains the input state of the device by
incorporating a weak latch into the input structure. This latch
maintains the input state until a minimum level of current (called the
overdrive current) is supplied to change the input state. This is
useful in bus applications where the bus is placed into a high
impedance state. The LVT22V10’s inputs, in this high impedance
situation, maintain valid logic levels until the bus is actively driven to
a new state.
Improved Fuse Verification Circuitry Increases
Reliability
Philips has developed a new means of testing the integrity of fuses,
both blown and intact fuses, which insures that all the fuses have
been correctly programmed and that each and every fuse – whether
“blown” or “intact” – is at the appropriate and optimal fuse
resistance. This dual verify scheme represents a significant
improvement over single reference voltage comparisons schemes
that have been used for bipolar devices since the late 1980s.
Detailed information on this feature is provided in an application note
entitled Dual Verify Technique Increases Reliability of PLDs
Programmable 3-stage Outputs
Each output has a 3-Stage output buffer with 3-State control. A
product term controls the buffer, allowing enable and disable to be a
function of any product of device inputs or output feedback. The
combinatorial output provides a bidirectional I/O pin, and may be
configured as a dedicated input if the buffer is always disabled.
Programmable Output Polarity
The polarity of each macro cell output can be Active-HIGH or
Active-LOW, either to match output signal needs or to reduce
product terms. Programmable polarity allows Boolean expressions
to be written in their most compact form (true or inverted), and the
output can still be of the desired polarity. It can also save
“DeMorganizing” efforts.
Selection is controlled by programmable bit S
0
in the Output Macro
Cell, and affects both registered and combinatorial outputs.
Selection is automatic, based on the design specification and pin
definitions. If the pin definition and output equation have the same
polarity, the output is programmed to be Active-HIGH (S
0
= 1).
Preset/Reset
For initialization, the LVT22V10 has additional Preset and Reset
product terms. These terms are connected to all registered outputs.
When the Synchronous Preset (SP) product term is asserted high,
the output registers will be loaded with a HIGH on the next
LOW-to-HIGH clock transition. When the Asynchronous Reset (AR)
product term is asserted high, the output registers will be
immediately loaded with a LOW, independent of the clock.
Note that Preset and Reset control the flip-flop, not the output pin.
The output level is determined by the output polarity selected.
Power-Up Reset
All flip-flops power-up to a logic LOW for predictable system
initialization. Outputs of the LVT22V10 will depend on the
programmed output polarity. The V
CC
rise must be monotonic and
the reset delay time is 1–10
μ
s maximum.
Security Fuse
After programming and verification, LVT22V10 designs can be
secured by programming the security fuse link. Once programmed,
this fuse defeats readback of the internal programmed pattern by a
device programmer, securing proprietary designs from competitors.
When the security fuse is programmed, the array will read as if
every fuse is programmed.
Quality and Testability
The LVT22V10 offers a very high level of built-in quality. Extra
programmable fuses provide a means of verifying performance of all
AC and DC parameters. In addition, this verifies programmability
and functionality of the device to provide the highest programming
and post-programming functional yields.
Technology
The BiCMOS LVT22V10 is fabricated with the Philips
Semiconductors process known as QUBiC. QUBiC combines an
advanced, state-of-the-art 1.0
μ
m (drawn feature size) CMOS
process with an ultra fast bipolar process to achieve superior speed
and drive capabilities. QUBiC incorporates three layers of Al/Cu
interconnects for reduced chip size, and our proven Ti-W fuse
technology ensures highest programming yields.
Programming
The LVT22V10 is fully supported by industry standard (JEDEC
compatible) PLD CAD tools, including Philips Semiconductors
SNAP design software package. ABEL
CUPL
and PALASM
90
design software packages also support the LVT22V10 architecture.
All packages allow Boolean and state equation entry formats, SNAP,
ABEL and CUPL also accept, as input, schematic capture format.
ABEL is a trademark of Data I/O Corp.
CUPL is a trademark of Logical Devices, Inc.
PALASM is a registered trademark of AMD Corp.
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| LVT22V10-DD | Fuse-Programmable PLD |
| LVT22V10-DN | Fuse-Programmable PLD |
| LW015F | DC-to-DC Voltage Converter |
| LC010 | DC-to-DC Voltage Converter |
| LC010A | DC-to-DC Voltage Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LVT22V10-DD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| LVT22V10-DN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| LVT240AU LVTH244U WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| LVT244B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.3-V ABT OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS |
| LVT245B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.3-V ABT OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS |
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