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參數(shù)資料
| 型號： | LVT22V10-7D |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | 3V high speed, universal PLD device |
| 中文描述： | OT PLD, 8.5 ns, PDSO24 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 185K |
| 代理商： | LVT22V10-7D |
Philips Semiconductors
Product specification
LVT22V10
3V high speed, universal PLD device
1998 Feb 10
14
INTERFACING IN MIXED 3V/5V SYSTEMS
3V Logic Driving 5V Logic
The LVT family has outputs that swing virtually between the power
supply rails, thereby allowing direct interfacing with TTL switching
levels.
When interfacing the outputs of any of our 3V logic ICs with
standard TTL-level logic inputs (bipolar or CMOS HCT), the output
levels from the 3V logic are sufficient to directly drive the 5V logic.
When driving CMOS-level devices (such as HC or AC), the output
voltage from the 3V logic is insufficient to ensure reliable operation.
This problem can be easily resolved by using a pull-up resistor at
the interface.
5V Logic Driving 3V Logic
Since the LVT ICs do not have protection diodes between their
inputs and V
CC
, the inputs of these devices can therefore withstand
higher levels than the supply voltage, and they can be directly
connected to 5V CMOS logic outputs. For the LVT family, the
combination of low power dissipation with the live insertion feature,
bus hold and full 5V input/output capability make this logic ideal for
3.3V backplane interfacing.
INTERFACING 3 VOLT AND 5 VOLT LOGIC
FROM
TO
METHOD
3V
to
5V
LVT Output
TTL Inputs
Direct
CMOS inputs
Pull-up
5V
to
3V
CMOS Rail
Totem-Pole
Open Drain
LVT Input
LVT Input
LVT Input
Direct
Direct
Pull-up
LVT22V10 METASTABLE HARDENED
CHARACTERISTICS
Metastable Hardened Characteristics
What is metastable hardened Philips Semiconductors uses the
term “metastable hardened” to describe a combination of two
characteristic features. The first is a patented Philips circuit that
prevents the outputs from glitching, oscillating, or remaining in the
linear region under any circumstances, including setup and hold
time violations. The second is the flip-flops’ inherent ability of
resolving the metastable condition. Philips provides complete data
on the LVT22V10’s metastable characteristics
With the LVT22V10, any tendency towards internal metastability is
resolved by Philips Semiconductors patented circuitry. If a
metastable event occurs within the flop, the only outward
manifestation of the event will be an increased clock-to-Q delay.
This delay is a function of the metastability characteristics of the
device, defined by
τ
and T
O
as described below. Since the outputs
never glitch, oscillate, or remain in the linear region, the only
metastable failure that can propagate further into the system is when
the next flip-flop in the system samples the LVT22V10’s output at
precisely the same time it is making a logic transition. By allowing
sufficient time for any increased clock-to-Q delay, propagation of
metastable failures can be avoided. The following design example
illustrates this concept.
Design Example
Suppose a designer wants to use the LVT22V10 for synchronizing
asynchronous data that is arriving at 2MHz (as measured by a
frequency counter), in a 3.3V system that has a clock frequency of
33MHz, at an ambient temperature of 25
°
C. She has decided that
she would like to sample the output of the LVT22V10 15ns after the
clock edge to ensure that any clock-to-Q delays that were the result
of the LVT22V10 internal metastability resolution circuitry have
completed and the outputs have transitioned. The MTBF for this
situation can be calculated by using the equation below:
MTBF = e(t’/
τ
)/T
O
F
C
F
1
In this formula, F
C
is the frequency of the clock, F
1
is the average
input event frequency, and t’ is the time after the clock pulse that the
output is sampled (t’ > T
CO
). T
O
and
τ
are device parameters
provided by the semiconductor manufacturer (refer to the following
table for the LVT22V10 metastability specifications). T
O
and
τ
are
derived from tests and can be most nearly be defined as follows:
τ
is
a function of the rate at which a latch in a metastable state resolves
that condition. T
O
is a function of the measurement of the propensity
of a latch to enter a metastable state. T
O
is also a normalization
constant, which is a very strong function of the normal propagation
delay of the device.
In this situation the F
1
will be twice the data frequency, or 4MHz,
because input events consist of both of low and high transitions.
Thus, in this case, F
C
is 33MHz, F
1
is 4MHz,
τ
is 317ps, t’ is 15ns,
and T
O
is 4.27
×
10
-3
seconds. Using the above formula the actual
MTBF for this situation is 1.26
×
10
9
seconds or 39 years for the
LVT22V10.
Summary
The Philips LVT22V10 has on-chip circuitry that completely
eliminates any output glitches, oscillations, or other output
anomalies associated with metastable conditions. For outputs that
are then used to generate clocks, control signals or other
asynchronous data this represents an unparalleled level of reliability
in a PLD. In addition, a complete set of metastability data is
provided, that allows designers the ability to design robust systems
where data is synchronously pipelined.
LVT22V10 VALUES FOR
τ
AND T
O
V
CC
0
°
C
25
°
C
75
°
C
τ
T
O
τ
T
O
τ
T
O
3.0V
3.3V
3.6V
829.00ps
358.00ps
237.00ps
1.16E–08
2.36E–04
2.66E–01
691.00ps
317.00ps
230.00ps
1.09E–07
4.27E–03
6.47E–01
429.00ps
329.00ps
250.00ps
2.27E–04
5.75E–03
1.13E+00
相關PDF資料 |
PDF描述 |
|---|---|
| LVT22V10-7N | 3V high speed, universal PLD device |
| LVT22V10B7A | 3V high speed, universal PLD device |
| LVT22V10BBA | Fuse-Programmable PLD |
| LVT22V10BDA | Fuse-Programmable PLD |
| LVT22V10-BN | Fuse-Programmable PLD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LVT22V10-7N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3V high speed, universal PLD device |
| LVT22V10B7A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3V high speed, universal PLD device |
| LVT22V10BBA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| LVT22V10BDA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| LVT22V10-BN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
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