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參數(shù)資料
| 型號： | LV8227LG |
| 元件分類： | 運動控制電子 |
| 英文描述： | UNIVERSAL MOTOR CONTROLLER, PBGA64 |
| 封裝： | 6 X 6 MM, FLGA-64 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 341K |
| 代理商： | LV8227LG |
LV8227LG
No.A0288-2/10
Electrical Characteristics at Ta = 25°C, VCC = 2.4V, VM = 3.6V, VG = 9.5V
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
Control circuit supply voltage
Control circuit supply voltage 1
ICC1
STALL pin: high (operating)
Conditions: ST1 and ST2 pins
15
A
Control circuit supply voltage 2
ICC2
STALL pin: low (standby mode)
1.0
A
Predriver supply voltage
Predriver supply voltage 1
IG1
STALL pin: high (operating)
Conditions: ST1 and ST2 pins
H bridge (2 channels): 88.2kHz
Three-phase driver (2 channels):176.4kHz
1.5
mA
Predriver supply voltage 2
IG2
STALL pin: low (standby mode)
1.0
A
STALL pin
High-level input voltage range
VSTALLH
VCC×0.8
VCC
V
Low-level input voltage range
VSTALLL
0
VCC×0.2
V
STALL pin pull-down resistor
RSTALL
0.33
0.6
1.0
M
Three-Phase Stepping Motor Block (spindle and sled) at Ta = 25°C, VCC = 2.4V, VM = 3.6V, VG = 9.5V
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
Output Block
Output on resistance
RonU, V, W
Sum of the high and low-side output on
resistances,VG = 9.5V
0.75
1.40
Decoder Input Pins
(UI1, 2 to WI1, 2 ST1, 2)
High-level input voltage range
VIH
VCC×0.8
VCC
V
Low-level input voltage range
VIL
0
VCC×0.2
V
ST pin pull-down resistor
RST
0.33
0.6
1.0
M
Comparator Block
Input offset voltage
VOFS
-5
+5
mV
Common-mode
input
voltage
range
VCM
0
VM
V
High-level output voltage
VOH
IO = -0.5mA
VCC×0.8
VCC
V
Low-level output voltage
VOL
IO = 0.5mA
0
VCC×0.2
V
PWM Pin (PWM1,2)
High-level input voltage range
VPWMH
VCC×0.8
VCC
V
Low-level input voltage range
VPWML
0
VCC×0.2
V
PWM input frequency
fPWMIN
88.2
176.4
kHz
H-Bridge Block (focus and tracking) at Ta = 25°C, VCC = 2.4V, VM = 3.6V, VG = 9.5V
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
Output Block
Output on resistance
Ron1,2
Sum of the high and low-side output on
resistances
VG = 9.5V
0.7
1.30
TRISE
Design target value
0.1
s
Output transmission delay time
(H bridge)
TFALL
Design target value
0.1
s
Minimum input pulse width
Tmin
Input pulse width: 89 ns
Design target value
70
ns
H-Bridge Input Pins (FI1, FI2, RI1, and RI2)
High-level input voltage range
VAIH
VCC×0.8
VCC
V
Low-level input voltage range
VAIL
0
VCC×0.2
V
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