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參數(shù)資料
| 型號(hào)： | LV8042LG |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | STEPPER MOTOR CONTROLLER, 0.6 A, PBGA68 |
| 封裝： | 6 X 6 MM, FLGA-68 |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 197K |
| 代理商： | LV8042LG |
LV8042LG
No.A0004-11/29
5ch
6ch (PWM) Setting/7ch (constant-current) Reference Voltage Setting
Register No.
Data
Nomenclature
Functions
Channel
D0
1
RG_SELECT 1
Register select 1
D1
1
RG_SELECT 2
Register select 1
D2
0 or 1
F/R5
Forward/reverse setting
D3
0 or 1
DECAY5
Current attenuation mode setting
5ch
PWM
D4
0 or 1
F/R6
Forward/reverse setting
D5
0 or 1
DECAY6
Current attenuation mode setting
6ch
PWM
D6
0 or 1
VSEN7_SELECT 1
7ch constant-current reference voltage select 1
D7
0 or 1
VSEN7_SELECT 1
7ch constant-current reference voltage select 2
7ch
Constant current
Serial Data Input Setting
Input DATA and SCLK after setting of STB = “L”. SCLK is not accepted in the state with STB = “H”.
Input DATA from D0 to D7 in this order. CLK performs data transmission at the rise edge and latches all data at rise
of STB after transmission of all data.
All of serial data is reset to “0” with ST = “L”. and at the voltage to cut VCC low voltage.
Timing to Reflect Serial Data to the Output
PWM mode (Applicable to 3, 4, 5, and 6ch)
Type 1: FR and DECAY settings during PWM drive are reflected simultaneously with the STB signal of data
latching.
STP mode (Applicable to 1, 2, 3, and 4ch)
Type 1: HOLD, RESET, CUT ENABLE settings and reference voltage setting are reflected simultaneously with the
STB signal of data latching.
Type 2: Forward/reverse (F/R) and excitation mode (MS) settings made during STEP setting are reflected at rise of the
next clock of data latching.
D0
DATA
SCLK
STB
ST
Status setting data latched
D1
D2
D3
D4
D5
D6
D7
CLK
STB
Data latch timing
STB timing
Type 1
Reflect at rise
CLK
STB
Data latch timing
Example: Two-phase excitation
Example: phases excitation
Type 2
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