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參數(shù)資料
| 型號(hào)： | LV4124W |
| 文件頁數(shù)： | 7/21頁 |
| 文件大小： | 277K |
| 代理商： | LV4124W |
No.6000-7/21
LV4124W
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
[Filter Characteristics]
NTSC 1.50 MHz
–15
–10
dB
Bandpass filter attenuation
ATBPF
PAL
2.00 MHZ
–15
–10
dB
NTSC 5.50 MHz
–7
–2
dB
PAL
6.80 MHz
–8
–3
dB
ATRAPN
NTSC
–40
–30
dB
Trap attenuation
ATRAPP
PAL
–40
–30
dB
R-Y and B-Y low-pass filter
DEMLPF
0.7
0.9
1.1
MHz
[Sync Separator Circuit and TG System]
Input synchronizing signal
amplitude sensitivity
WSSEP
2.0
μs
Sync separator circuit input
sensitivity
VSSEP
40
60
mV
TDSYL
430
630
830
ns
Sync separator circuit output
delay
TDSYH
4.7
5.0
5.3
μs
HPLLN
NTSC
±500
Hz
Horizontal pull-in range
HPLLP
PAL
±500
Hz
Continued on next page.
Input SIG5 (VL = 0 mV) to (A) and SIG1
(0 dB) to (B). Take the T53 chrominance
amplitude when the center frequency
(3.58 and 4.43 MHz) is input to be 0 dB,
and measure the T53 output attenuation
for the frequencies listed at the right.
Input SIG7 (0 dB, 3.58 and 4.43 MHz) to (A)
and measure the T44 output with a spectrum
analyzer. Taking the T44 amplitude in Y/C
mode to be 0 dB, determine the attenuation in
composite input mode.
Input SIG5 (VL = 150 mV) to (A) and SIG2 (0 dB, 3.58 MHz
+ 100 kHz) to (B). Take the T44 output 100 kHz component
am plitude at this time to be 0 dB, and determine the
frequency at which the output beat component is reduced by
3 dB when the SIG2 frequency is increased from 3.58 MHz.
Input SIG5 (VL = 0 mV, VS = 143 mV, variable WS) to (A)
and verify synchronization with the T23 HD output.
Determine the value of WS at the point synchronization with
the T23 HD output is lost when the SIG5 WS is gradually
made narrower starting at 4.7 μs.
Input SIG5 (VL = 0 mV, WS = 4.7 μs, variable VS) to (A) and
verify synchronization with the T23 HD output. Determine the
value of VS at the point synchronization with the T23 HD
output is lost when the SIG5 VS is gradually reduced starting
at 143 mV.
Input SIG5 (VL = 0 mV, WS = 4.7 μs, VS = 143 mV) to (A)
and measure the delay time with respect to the T12 RPD
output. Here, TDSYL is the delay from the fall of the input
HSYNC signal to the fall of the T12 RPD output, and TDSYH
is the delay from the rise of the input HSYNC signal to the
rise of the T12 RPD output.
Input SIG5 (VL = 0 mV, WS = 4.7 μs, VS =
143 mV, variable horizontal frequency) to (A)
and verify synchronization withthe T23 HD
output. Determine the frequency fH at which
synchronization is achieved when the SIG5
horizontal frequency is varied starting from the
state where I/O synchronization is lost.
Calculate HPLLN = fH – 15734 and HPLLP =
fH – 15625.
AC Characteristics (4)
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