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參數(shù)資料
| 型號(hào)： | LV3400M |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | FM Multiplex Filter(FM多路濾波器) |
| 中文描述： | 調(diào)頻多重過濾器（調(diào)頻多路濾波器） |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 90K |
| 代理商： | LV3400M |
No. 4862-2/4
LV3400M
Operating Conditions
at Ta = 25°C
Operating Characteristics
at Ta = 25°C, V
CC
= 5 V, f
CK
= 3.6 MHz, V
CK
= 1 Vp-p
Reference Characteristics
Pin Functions
Usage Notes
1. Pins 4 to 9 and pin 13 are left open in normal use.
2. The clock should be taken from the decoder (LC72700) clock output pin and input to pin through a capacitor of about
100 pF. Spurious radiation from the clock line can be reduced by inserting a resistor in the line and thus smoothing
the rising and falling edges. This signal is then input to pin 12 through a capacitor.
Parameter
Symbol
Conditions
Ratings
Unit
Operating supply voltage range
V
CC
4.5 to 5.5
V
A composite signal corresponding to a 100%
FM modulation level
200 to 300
mVrms
Input signal voltage range
V
IN
f
IN
= 76 kHz, CW
8 to 30
mVrms
Clock frequency
f
CK
V
CK
3.60
MHz
Clock input voltage
1.0 to V
CC
Vp-p
Parameter
Symbol
Conditions
min
typ
max
Unit
Current drain
I
CCO
V
2
Rin3
The pin 14 current for a no-signal input to V
IN
The pin 2 voltage for a no-signal input to V
IN
The pin 3 input resistance
3.8
6
8
mA
SCF block common voltage
2.1
2.3
2.5
V
k
k
Signal input resistance
36
Clock input resistance
Rin12
The pin 12 input resistance
100
[MSK Output]
The input level such that an MSK output with the same
frequency is acquired when a 76-kHz CW is applied
as V
IN
.
MSK input sensitivity
V
3S
4
mVrms
MSK output high level
V
10H
V
10L
V
IN
= 76 kHz, 4 mVrms, CW
4
V
MSK output low level
0.4
V
Parameter
Symbol
Conditions
Ratings
Unit
AAF cutoff frequency
300
kHz
HPF corner frequency
54
kHz
LPF cutoff frequency
125
kHz
BPF center frequency
76
kHz
BPF -3 dB frequency
19
kHz
Maximum in-band group delay time difference
±5
μs
PinNo.
Symbol
Description
1
GND
Ground
2
VCOM
SCF block common. A decoupling capacitor must be used.
3
SIG. IN
Signal input. Input an FM modulated signal (composite signal). A modulated signal between 200 and 300 mVrms should be
input. The input sensitivity for a pure 76-kHz signal is 4 mVrms or lower.
10
MSK OUT
MSK output (CMOS output)
Limiter reference voltage. A low-pass filter is formed by the internal resistance (which is about 10 k
) and an external capacitor.
3.6-MHz clock input. The DC bias at the CMOS inverter input, to which a 100-k
feedback resistor is connected, is about
V
CC
/2. The clock signal is input through a capacitor.
The clock output that was wave-shaped by an inverter. This pin is normally left open.
11
V
REF
12
CLK IN
13
CLK OUT
14
V
CC
Power supply
4 to 9
NC, Test PIN
This pin must be left open.
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