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參數(shù)資料
| 型號： | LV2151V |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 2.0 GHz PLL Frequency Synthesizer IC(2.0 GHz鎖相環(huán)頻率合成器) |
| 中文描述： | 2.0 GHz PLL頻率合成器集成電路（2.0千兆赫鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 139K |
| 代理商： | LV2151V |
Serial Data Description
(1) Programmable Counter and Test Mode
Bit “ADD(Latch Address Data)” = 1
1. Programmable Counter
Bits P0 to P16 determine programmable divider ratios. Binary value with P0 as the LSB.
The division ratio can be set in the range of 4032 to 131071.
Ex. Settable division ratio factor is 8192
2. Test Mode
TS0 and TS1 are testing bits. These bits must normally be set to 0.
(2) Reference Counter and Other Control
ADD is the latch address bit. This bit must be set to 0.
1. Reference Counter
Bits R0 to R11 determine programmable divider ratios. Binary value with R0 as the LSB.
The division ratio can be set in the range of 20 to 4095.
Ex. Settable division ratio factor is 2048 (“*” = Don’t care)
2. Phase Comparator Output Control
Bit CPD is phase comparator polarity switching data.
Fig.1
3. Unlock Detection Control
ULD is used to control the signal length which determines whether or not the PLL is locked. PLL is determined as
unlocked if a phase error signal longer than that in the table below is detected.
No. 6145-6/10
LV2151V
CPD
Phase comparator polarity
0
(1) Shown Fig.1
1
(2) Shown Fig.1
ULD
Thresholds
fXIN = 10.24 MHz
0
±4/fXIN
390 ns
1
±8/fXIN
780 ns
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
1
0
0
0
0
0
0
0
0
0
0
0
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