參數(shù)資料
型號: LV2105V
廠商: Sanyo Electric Co.,Ltd.
英文描述: 530Mhz PLL Frequency Synthesizers LSI(530Mhz 鎖相環(huán)頻率合成器)
中文描述: 530Mhz鎖相環(huán)頻率合成器大規(guī)模集成電路(530Mhz鎖相環(huán)頻率合成器)
文件頁數(shù): 5/7頁
文件大小: 74K
代理商: LV2105V
Continued from preceding page.
Pin No.
(3)
Control block/data
Power save data
PS
Internal block
.
Data that sets the power save mode on or off
(4)
Output port data
OUT
.
Data that sets the output of the output port
(5)
Charge pump ON/OFF data
CP
.
Data that sets whether to operate the charge pump or to implement
high impedance.
(6)
LSI test data TS1
.
LSI test mode switch.
Set TS1 = 0. Normally, the TEST pin is connected to GND.
.
Data that sets the division ratio of the programmable divider.
Binary value with FP0 as the LSB. However, the settable division ratio
factor is up to 131071.
(7)
Programmable divider data
FP0 to FP16
PS data
0
1
Item
Power save mode
Normal operation
OUT data OUT Pin
0
1
Low
High
CP data
0
1
Item
High impedance
Normal operation
Pin Functions
Pin Name
XIN
CL
DI
CE
V
CC
R
PI
GND R
TEST
CP
PDP
Pin Function
I/O Style
1
2
3
4
5
6
7
8
9
10
Reference signal input pin (Xtal oscillation pin)
Data input pin
Data input pin
Data input pin
ECL block power supply pin
Comparison signal input pin
ECL block GND pin
LSI test pin. Must be connected to GND.
Built-in charge pump output pin
Phase comparator output for an external charge
pump.
If not to be used, connect to GND.
Phase comparator output for an external charge
pump.
GND pin for circuits except the ECL block
Power supply pin for circuits except the ECL block
Phase error output pin for phase comparator
Output port pin for switching external SW.
Output pin for Xtal oscillation
CMOS input
CMOS, No pull-down
CMOS, No pull-down
CMOS, No pull-down
BIP input
CMOS, No pull-down
BIP
CMOS, Nch open-drain output
11
PDN
CMOS output
12
13
14
15
16
GND D
V
CC
D
PE
OUT
XOUT
CMOS output
BIP NPN open-collector output
CMOS output
LV2105V
No.4876 -5/7
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