參數(shù)資料
型號(hào)： LUCL9311AP-D
英文描述： Line Interface and Line Access Circuit Full-Feature SLIC with High Longitudinal Balance, Ringing Relay,and GR-909 Test Access
中文描述： 線路接口和線路接入電路全功能用戶接口高縱向平衡，振鈴繼電器，和GR - 909測(cè)試訪問
文件頁數(shù)： 23/50頁
文件大小： 852K
代理商： LUCL9311AP-D
Data Sheet
July 2001
Ringing Relay, and GR-909 Test Access
L9311 Full-Feature SLIC with High Longitudinal Balance,
Agere Systems Inc.
23
Electrical Characteristics
(continued)
Logic Inputs and Outputs, V
DD
= 5.0 V
Table 12. Logic Inputs and Outputs
Timing Requirements
Table 13. Timing Requirements
Data control is via a parallel latched data control scheme. Data latches are edge-level sensitive. Data is latched in
when the LATCH control input goes low. Data must be set up t
SU
ns before LATCH goes low and held t
HL
ns after
LATCH goes high. While LATCH is low, the user should not change the data control inputs at B0, B1, B2, and B3.
The data control inputs at B0, B1, B2, and B3 may only be changed when LATCH is high. NSTAT supervision out-
put is not controlled by the LATCH control input.
12-3526(F)
Figure 4. Timing Requirements
Parameter
Symbol
V
IL
V
IH
Min
Typ
Max
Unit
Input Voltages:
Low Level
High Level
Input Current:
Low Level (V
DD
= 5.25 V, V
I
= 0.4 V)
High Level (V
DD
= 5.25 V, V
I
= 2.4 V)
Output Voltages (CMOS):
Low Level (V
DD
= 4.75 V, I
OL
= 180
μ
A)
High Level (V
DD
= 4.75 V, I
OH
=
–
20
μ
A)
–
0.5
2.0
0.4
2.4
0.7
V
DD
V
V
I
IL
I
IH
—
—
—
—
±
50
±
50
μ
A
μ
A
V
OL
V
OH
0
2.4
0.2
—
0.4
V
DD
V
V
Parameter
Symbol
t
SU
t
HL
Min
200
50
Typ
—
—
Max
—
—
Unit
ns
ns
Minimum Setup Time from B0, B1, B2, B3 to LATCH
Minimum Hold Time from LATCH to B0, B1, B2, B3
t
SU
t
HL
LATCH
B0, B1,
B2, B3
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