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參數(shù)資料
| 型號： | LUC4AB01 |
| 廠商： | Lineage Power |
| 英文描述： | ATM Buffer Manager (ABM)(ATM緩沖管理器 (ABM)) |
| 中文描述： | 緩沖區(qū)管理器自動柜員機（ABM）的（自動柜員機緩沖管理器（反導條約）） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 182K |
| 代理商： | LUC4AB01 |
Advance Product Brief
March 1997
LUC4AB01
ATM Buffer Manager (ABM)
S
LUCENT TECHNOLOGIES—PROPRIETARY
Use pursuant to Company Instructions
Introduction
The ABM IC is part of the ATLANTA chip set consist-
ing of four devices that provide a highly integrated,
innovative, and complete VLSI solution for implement-
ing the ATM layer core of an ATM switch system. The
chip set enables construction of high-performance,
feature-rich, and cost-effective ATM switches, scalable
over a wide range of switching capacities. This docu-
ment discusses the ABM device.
Features
I
Provides input/output (bidirectional) queue manage-
ment for an N x N switch fabric (up to 25 Gbits/s
capacity) and up to 31 MPHY ports.
— Handles full-duplex aggregate ATM traffic up to
622 Mbits/s (ingress and egress).
— Queues up to 32K ATM cells in external memory
using standard synchronous SRAMs, organized
in a shared output buffered architecture*.
— Supports four delay priorities per queue.
I
Uses programmable, weighted, round-robin algo-
rithm for flexibility in scheduling delay priority ser-
vice (can default to strict priority service).
I
On egress, provides programmable rate scheduling
of output queues for MPHY ports (from 1.2 Mbits/s
to 622 Mbits/s). Can also accommodate variable
rate PHY ports (e.g., SAR devices).
I
Performs multicasting (on egress side) for up to 30
MPHY output ports and one CPU port.
I
Incorporates an innovative adaptive dynamic
thresholding (ADT) algorithm for maximizing buffer
efficiency while ensuring fairness.
I
Provides range of congestion management options
and support for ABR.
— Supports nonblocking backpressure feedback
from an external switch fabric.
— Selective cell discard (CLP1, CLP0+1).
— Optional EFCI marking (SEFCI on a per-connec-
tion basis) and support for CI/NI marking.
— Optional EPD and PPD support.
— Independent, configurable dynamic thresholds
available for each delay priority level to trigger
congestion management options. Can default to
static thresholding.
I
Supplies buffer congestion data to support an
optional external ER calculation engine for ABR flow
control.
I
Maintains an extensive variety of counters for statis-
tics gathering, facilitating network management soft-
ware.
I
Supports simultaneous links with dual-switch fabric
cards to facilitate redundant fabric operation.
I
Can be used in conjunction with LUC4AU01 ALM IC
to provide a complete stand-alone two-chip solution
for:
— A 4 x 4 at 155 Mbits/s ATM shared memory
switch.
— A 25 x 25 at 25 Mbits/s ATM shared memory
switch.
— ATM multiplexor/concentrator applications.
I
Can be used in conjunction with an external switch
fabric (LUC4AS01 ASX and LUC4AC01 ACE ICs,
part of the ATLANTA chip set) to provide a scalable,
nonblocking switch solution.
I
Provides a generic, Intel
or Motorola
compatible,
16-bit microprocessor interface for configuration,
statistics, and maintenance.
I
Supports a scalable external memory interface with
synchronous SRAMs (20 ns cycle time).
I
Facilitates circuit board testing with on-chip IEEE
§
standard boundary scan.
I
Fabricated as a low-power, monolithic IC in 0.5
μ
m,
3.3 V CMOS technology, with 5 V-tolerant and TTL-
level compatible I/O.
I
Available in 352-pin PBGA package.
§
Intel
Motorola
IEEE
Electronics Engineers, Inc.
is a registered trademark of Intel Corporation.
is a registered trademark of Motorola, Inc.
is a registered trademark of The Institute of Electrical and
* In half-duplex operation, the ABM can queue up to 64K ATM cells
in external memory using standard synchronous SRAMs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LUC4AB01388BAC4-DB | 制造商:Agere Systems 功能描述: |
| LUC4AB01BAC4DB | 制造商:LUCENT 功能描述:* |
| LUC4AS01-BC7-DB | 制造商:Agere Systems 功能描述: |
| LUC4AU01SC5DB | 制造商:LUCENT 功能描述:* |
| LUC4AU01-SC5-DB | 制造商:Agere Systems 功能描述: |
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