power requireMenTs The l denotes the specifications wh" />
參數(shù)資料
型號: LTM9011CY-14#PBF
廠商: Linear Technology
文件頁數(shù): 37/40頁
文件大?。?/td> 0K
描述: IC ADC 14BIT UMODULE 140BGA
標(biāo)準(zhǔn)包裝: 210
系列: µModule®
位數(shù): 14
采樣率(每秒): 125M
數(shù)據(jù)接口: Serial LVDS
轉(zhuǎn)換器數(shù)目: 8
功率耗散(最大): 1.33W
電壓電源: 模擬和數(shù)字
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 140-BFBGA
供應(yīng)商設(shè)備封裝: 140-BGA(11.25x9)
包裝: 托盤
輸入數(shù)目和類型: 8 Differential; 8 Single-Ended
LTM9011-14/
LTM9010-14/LTM9009-14
6
9009101114fa
power requireMenTs The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
LTM9011-14
LTM9010-14
LTM9009-14
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
VDD
Analog Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
OVDD
Output Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
IVDD
Analog Supply Current
Sine Wave Input
l
582
632
476
508
395
450
mA
IOVDD
Digital Supply Current
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
l
54
98
62
108
52
96
62
106
50
94
58
104
mA
PDISS
Power Dissipation
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
l
1145
1224
1249
1332
950
1030
1026
1105
801
880
914
997
mW
PSLEEP
Sleep Mode Power
2
mW
PNAP
Nap Mode Power
170
mW
PDIFFCLK Power Decrease With Single-Ended Encode Mode Enabled
(No Decrease for Sleep Mode)
40
mW
TiMing characTerisTics The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
LTM9011-14
LTM9010-14
LTM9009-14
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
fS
Sampling Frequency
(Notes 10,11)
l
5
125
5
105
5
80
MHz
tENCL
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
3.8
2
4
100
4.52
2
4.76
100
5.93
2
6.25
100
ns
tENCH
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
3.8
2
4
100
4.52
2
4.76
100
5.93
2
6.25
100
ns
tAP
Sample-and-Hold
Acquisition Delay Time
0
ns
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output)
tSER
Serial Data Bit Period
2-Lanes, 16-Bit Serialization
2-Lanes, 14-Bit Serialization
2-Lanes, 12-Bit Serialization
1-Lane, 16-Bit Serialization
1-Lane, 14-Bit Serialization
1-Lane, 12-Bit Serialization
1/(8 fS)
1/(7 fS)
1/(6 fS)
1/(16 fS)
1/(14 fS)
1/(12 fS)
s
tFRAME
FR to DCO Delay
(Note 8)
l
0.35 tSER
0.5 tSER
0.65 tSER
s
tDATA
DATA to DCO Delay
(Note 8)
l
0.35 tSER
0.5 tSER
0.65 tSER
s
tPD
Propagation Delay
(Note 8)
l
0.7n + 2 tSER 1.1n + 2 tSER 1.5n + 2 tSER
s
tR
Output Rise Time
Data, DCO, FR, 20% to 80%
0.17
ns
tF
Output Fall Time
Data, DCO, FR, 20% to 80%
0.17
ns
DCO Cycle-Cycle Jitter
tSER = 1ns
60
psP-P
Pipeline Latency
6
Cycles
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