參數(shù)資料
型號(hào): LTM4600HVIV#TRPBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 17 A SWITCHING REGULATOR, BGA104
封裝: 15 X 15 MM, ROHS COMPLIANT, MO-222, LGA-104
文件頁數(shù): 6/24頁
文件大?。?/td> 351K
代理商: LTM4600HVIV#TRPBF
LTM4600HV
14
4600hvfd
explanation of the analysis for the thermal models, and the
derating curves. Tables 3 and 4 provide a summary of the
equivalent θJA for the noted conditions. These equivalent
θJA parameters are correlated to the measure values, and
improved with air-ow. The case temperature is maintained
at 100°C or below for the derating curves. This allows for
4W maximum power dissipation in the total module with
top and bottom heatsinking, and 2W power dissipation
through the top of the module with an approximate θJC
between 6°C/W to 9°C/W. This equates to a total of 124°C
at the junction of the device.
Safety Considerations
The LTM4600HV modules do not provide isolation from
VIN to VOUT. There is no internal fuse. If required, a slow
blow fuse with a rating twice the maximum input current
should be provided to protect each unit from catastrophic
failure.
Layout Checklist/Example
The high integration of the LTM4600HV makes the PCB
board layout very simple and easy. However, to optimize
its electrical and thermal performance, some layout con-
siderations are still necessary.
Use large PCB copper areas for high current path, in-
cluding VIN, PGND and VOUT. It helps to minimize the
PCB conduction loss and thermal stress
Place high frequency ceramic input and output capaci-
tors next to the VIN, PGND and VOUT pins to minimize
high frequency noise
Place a dedicated power ground layer underneath
the unit
To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers
Do not put vias directly on pad unless they are capped.
Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to PGND underneath the unit
Figure 20 gives a good example of the recommended
layout.
In the application where the light load efciency is im-
portant, tying the FCB pin above 0.6V threshold enables
discontinuous operation where the bottom MOSFET turns
off when inductor current reverses. Therefore, the conduc-
tion loss is minimized and light load efciency is improved.
The penalty is that the controller may skip cycle and the
output voltage ripple increases at light load.
Paralleling Operation with Load Sharing
Two or more LTM4600HV modules can be paralleled to
provide higher than 10A output current. Figure 7 shows
the necessary interconnection between two paralleled
modules. The OPTI-LOOP current mode control ensures
good current sharing among modules to balance the ther-
mal stress. The new feedback equation for two or more
LTM4600HVs in parallel is:
VOUT = 0.6V
100k
N
+RSET
RSET
where N is the number of LTM4600HVs in parallel.
Figure 7. Parallel Two μModules with Load Sharing
VIN
VOUT
VIN
VOUT
(20AMAX)
4600hv F07
LTM4600HV
PGND
SGND
COMP VOSET
RSET
VIN
VOUT
LTM4600HV
PGND
SGND
COMP VOSET
OPTI-LOOP is a trademark of Linear Technology Corporation.
Thermal Considerations and Output Current Derating
The power loss curves in Figures 8 and 15 can be used
in coordination with the load current derating curves in
Figures 9 to 14, and Figures 16 to 19 for calculating an
approximate θJA for the module with various heatsink-
ing methods. Thermal models are derived from several
temperature measurements at the bench, and thermal
modeling analysis. Application Note 103 provides a detailed
APPLICATIONS INFORMATION
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