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參數(shù)資料
| 型號(hào)： | LTI2911IDDB-1#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | 3 X 2 MM, LEAD FREE, PLASTIC, MO-229, DFN-8 |
| 文件頁(yè)數(shù)： | 19/20頁(yè) |
| 文件大?。?/td> | 245K |
| 代理商： | LTI2911IDDB-1#TRPBF |
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LTC2911
8
2911f
TIMING DIAGRAMS
Input Valid to Latch Enable
Setup and Hold Timing
tRST
VTMR(LATCH)
VTMR(LATCH) +
VTMR(LATCH)
2911 TD04
t > tSU,MON
1V
RST
ADJ, V1, V2
TMR
VRTX
tSU,MON
tHD,MON
LATCH IN
NOTE: FOR THE LTC2911-5, V1 LOW RESETS RST TO A LOW STATE
–3% OVERDRIVE
INPUT RETURNING TO ABOVE VRTX
FOR t > tSU,MON, RST PIN STAYS HIGH
3% OVERDRIVE
MARGINING
POWER UP
Input Valid to Latch Release
Setup Timing
Input Invalid to Latch Enable
Setup and Hold Timing
Input Invalid to Latch
Release Setup Timing
TMR
RST
ADJ, V1, V2
tSU,MON
tUV
tHD,MON
LATCH IN
NOTE: FOR THE LTC2911-5, V1 LOW RESETS RST TO A LOW STATE
VTMR(LATCH)
VRTX
1V
VTMR(LATCH) +
VTMR(LATCH)
t > tSU,MON
VRTX
–3% OVERDRIVE
2911 TD05
–3% OVERDRIVE
3% OVERDRIVE
MARGINING
INPUT RETURNING TO BELOW VRTX
FOR t > tSU,MON, RST PIN STAYS LOW
Undervoltage and Reset Timing
Latch Release to RST Low Timing
VRTX
tUV
tRST
1.0V
2911 TD01
VX
RST
TMR
0.4V
1.0V
2911 TD02
NOTE: ADJ FORCED LOW BEFORE TMR RELEASE
tP,LR
Power-Fail Timing
PFI
VPFT
tP,PF
1.0V
2911 TD03
PFO
Latching RST High
Latching RST Low
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| LTI2911IDDB-3#TRMPBF | POWER SUPPLY SUPPORT CKT, PDSO8 |
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| LTC2911CDDB-4#TRPBF | POWER SUPPLY SUPPORT CKT, PDSO8 |
| LTC2911CDDB-5#TR | POWER SUPPLY SUPPORT CKT, PDSO8 |
| LTC2911CTS8-2#TRPBF | POWER SUPPLY SUPPORT CKT, PDSO8 |
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參數(shù)描述 |
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