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參數(shù)資料
型號(hào)： LTC6994MPS6-2#TRMPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 7/26頁(yè)
文件大?。?/td> 0K
描述： IC DELAY LINE SOT-23-6
特色產(chǎn)品： TimerBlox?
標(biāo)準(zhǔn)包裝： 500
系列： TimerBlox®
功能： 可編程
可用的總延遲： 1µs ~ 33.6s
獨(dú)立延遲數(shù)： 1
電源電壓： 2.25 V ~ 5.5 V
工作溫度： -55°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： SOT-23-6 細(xì)型，TSOT-23-6
供應(yīng)商設(shè)備封裝： TSOT-23-6
包裝： 帶卷 (TR)
配用： DC1562A-E-ND - BOARD EVAL LTC6992-3
LTC6994-1/LTC6994-2
15
699412fb
operaTion
Changing DIVCODE After Start-Up
Following start-up, the A/D converter will continue
monitoring VDIV for changes. Changes to DIVCODE will
be recognized slowly, as the LTC6994 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
tDIVCODE = 16 (DIVCODE + 6) tMASTER
A change in DIVCODE will not be recognized until it is
stable, and will not pass through intermediate codes. A
digital filter is used to guarantee the DIVCODE has settled
to a new value before making changes to the output. How-
ever, if the delay timing is active during the transition, the
actual delay can take on a value between the two settings.
Start-Up Time
When power is first applied, the power-on reset (POR)
circuit will initiate the start-up time, tSTART. The OUT pin
is held low during this time and the IN pin has no control
over the output. The typical value for tSTART ranges from
0.5msto8msdependingonthemasteroscillatorfrequency
(independent of NDIV):
tSTART(TYP) = 500 tMASTER
During start-up, the DIV pin A/D converter must determine
the correct DIVCODE before the LTC6994 can respond
to an input. The start-up time may increase if the supply
or DIV pin voltages are not stable. For this reason, it is
recommended to minimize the capacitance on the DIV
pin so it will properly track V+. Less than 100pF will not
extend the start-up time.
At the end of tSTART the DIVCODE and IN pin settings are
recognized, and the state of the IN pin is transferred to the
output (without additional delay). If IN is high at the end of
tSTART, OUT will go high. Otherwise OUT will remain low.
The LTC6994-2 with POL = 1 is the exception because it
inverts the signal. At this point, the LTC6994 is ready to
respond to rising/falling edges on the input.
DIV
500mV/DIV
IN
2V/DIV
OUT
2V/DIV
LTC6994-1
V+ = 3.3V
RSET = 200k
500s/DIV
699412 F07a
512s
256s
4s
Figure 7a. DIVCODE Change from 0 to 2
DIV
500mV/DIV
IN
2V/DIV
OUT
2V/DIV
LTC6994-1
V+ = 3.3V
RSET = 200k
500s/DIV
699412 F07b
256s
4s
512s
Figure 7b. DIVCODE Change from 2 to 0
IN
V+
OUT
tSTART
(IN IGNORED)
tPD
699412 F08
IF IN = 1 AT END OF tSTART*
IF IN = 0 AT END OF tSTART*
*LTC6994-2 WITH POL = 1 INVERTS THE OUTPUT
Figure 8. Start-Up Timing Diagram
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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