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參數(shù)資料
| 型號： | LTC6993MPS6-4#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/26頁 |
| 文件大小： | 0K |
| 描述： | IC MULTIVIBRATOR MONO TSOT23-6 |
| 特色產(chǎn)品： | TimerBlox? |
| 標準包裝： | 2,500 |
| 系列： | LTC®6993 |
| 邏輯類型： | 單穩(wěn)態(tài) |
| 獨立電路： | 1 |
| 施密特觸發(fā)器輸入： | 無 |
| 傳輸延遲： | 11ns |
| 輸出電流高，低： | 16mA，16mA |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 細型，TSOT-23-6 |
| 供應商設備封裝： | TSOT-23-6 |
| 包裝： | 帶卷 (TR) |
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
15
69931234fb
OPERATION
Changing DIVCODE After Start-Up
Following start-up, the A/D converter will continue
monitoring VDIV for changes. Changes to DIVCODE will
be recognized slowly, as the LTC6993 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
tDIVCODE = 16 (DIVCODE + 6) tMASTER
A change in DIVCODE will not be recognized until it is
stable, and will not pass through intermediate codes. A
digital filter is used to guarantee the DIVCODE has settled
to a new value before making changes to the output. How-
ever, if the output pulse is active during the transition, the
pulse width can take on a value between the two settings.
Start-Up Time
When power is first applied, the power-on reset (POR)
circuit will initiate the start-up time, tSTART. The OUT pin
is held low during this time. The typical value for tSTART
ranges from 0.5ms to 8ms depending on the master oscil-
lator frequency (independent of NDIV):
tSTART(TYP) = 500 tMASTER
During start-up, the DIV pin A/D converter must deter-
mine the correct DIVCODE before an output pulse can be
generated. The start-up time may increase if the supply
or DIV pin voltages are not stable. For this reason, it is
recommended to minimize the capacitance on the DIV
pin so it will properly track V+. Less than 100pF will not
extend the start-up time.
TheDIVCODEsettingisrecognizedattheendofthestartup
up. If POL = 1, the output will transition high. Otherwise
(if POL = 0) OUT simply remains low. At this point, the
LTC6993 is ready to respond to rising/falling edges on
the TRIG input.
Figure 5a. DIVCODE Change from 0 to 2
Figure 5b. DIVCODE Change from 2 to 0
Figure 6. Start-Up Timing Diagram
DIV
500mV/DIV
TRIG
2V/DIV
OUT
2V/DIV
LTC6993-1
V+ = 3.3V
RSET = 200k
200s/DIV
69931234 F05a
512s
256s
4s
DIV
500mV/DIV
TRIG
2V/DIV
OUT
2V/DIV
LTC6993-1
V+ = 3.3V
RSET = 200k
200s/DIV
69931234 F05b
512s
256s
4s
TRIG
V+
OUT
tSTART
(TRIG IGNORED)
tOUT
POL = 1
69931234 F06
POL = 0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LTC6994-1 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:TimerBlox: Delay Block/ Debouncer |
| LTC6994-2 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:TimerBlox: Delay Block/ Debouncer |
| LTC6994CDCB-1#PBF | 制造商:Linear Technology 功能描述:DELAY BLOCK/DEBOUNCER 5.5V DFN-6 制造商:Linear Technology 功能描述:DELAY BLOCK/DEBOUNCER, 5.5V, DFN-6 制造商:Linear Technology 功能描述:SC-Timing, Cut Tape Delay with Rising or Falling Edge Trigger 制造商:Linear Technology 功能描述:DELAY BLOCK/DEBOUNCER, 5.5V, DFN-6, Operating Mode:Monostable, Supply Voltage Min:2.25V, Supply Voltage Max:5.5V, Digital IC Case Style:DFN, No. of Pins:6, Operating Temperature Min:0C, Operating Temperature Max:70C , RoHS Compliant: Yes |
| LTC6994CDCB-1#TRMPBF | 功能描述:IC DELAY LINE 6-DFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:TimerBlox® 標準包裝:2,500 系列:- 標片/步級數(shù):- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:14-SOIC 包裝:帶卷 (TR) |
| LTC6994CDCB-1#TRPBF | 功能描述:IC DELAY LINE 6-DFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 延遲線 系列:TimerBlox® 標準包裝:2,500 系列:- 標片/步級數(shù):- 功能:多個，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:14-SOIC 包裝:帶卷 (TR) |
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