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參數(shù)資料
| 型號(hào)： | LTC6992MPS6-4#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC PWM VOLT CTLR TSOT23-6 |
| 特色產(chǎn)品： | TimerBlox? |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | TimerBlox® |
| 類型： | 振蕩器 - 硅 |
| 頻率： | 3.81Hz ~ 1MHz |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 電流 - 電源： | 365µA |
| 工作溫度： | -55°C ~ 125°C |
| 封裝/外殼： | SOT-23-6 細(xì)型，TSOT-23-6 |
| 包裝： | 帶卷 (TR) |
| 供應(yīng)商設(shè)備封裝： | TSOT-23-6 |
| 安裝類型： | 表面貼裝 |
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LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
14
69921234fc
operaTion
The LTC6992 is built around a master oscillator with a
1MHz maximum frequency. The oscillator is controlled
by the SET pin current (ISET) and voltage (VSET), with a
1MHz 50k conversion factor that is accurate to ±0.8%
under typical conditions.
fMASTER =
1
tMASTER
= 1MHz 50k
ISET
VSET
A feedback loop maintains VSET at 1V ±30mV, leaving ISET
as the primary means of controlling the output frequency.
The simplest way to generate ISET is to connect a resistor
(RSET) between SET and GND, such that ISET = VSET/RSET.
The master oscillator equation reduces to:
fMASTER =
1
tMASTER
=
1MHz 50k
RSET
From this equation, it is clear that VSET drift will not affect
theoutputfrequencywhenusingasingleprogramresistor
(RSET). Error sources are limited to RSET tolerance and
the inherent frequency accuracy
fOUT of the LTC6992.
RSET may range from 50k to 800k (equivalent to ISET
between 1.25μA and 20μA).
The LTC6992 includes a programmable frequency divider
which can further divide the frequency by 1, 4, 16, 64,
256, 1024, 4096 or 16384 before driving the OUT pin.
The divider ratio NDIV is set by a resistor divider attached
to the DIV pin.
fOUT =
1
tOUT
=
1MHz 50k
NDIV
ISET
VSET
With RSET in place of VSET/ISET the equation reduces to:
fOUT =
1
tOUT
=
1MHz 50k
NDIV RSET
DIVCODE
TheDIVpinconnectstoaninternal,V+referenced4-bitA/D
converter that determines the DIVCODE value. DIVCODE
programs two settings on the LTC6992:
1. DIVCODE determines the output frequency divider set-
ting, NDIV.
2. DIVCODE determines the output polarity, via the POL
bit.
VDIV may be generated by a resistor divider between V+
and GND as shown in Figure 1.
Figure 1. Simple Technique for Setting DIVCODE
6992 F01
LTC6992
V+
DIV
GND
R1
R2
2.25V TO 5.5V
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相關(guān)代理商/技術(shù)參數(shù) |
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| LTC6993-1 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:TimerBlox: Monostable |
| LTC6993-2 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:TimerBlox: Monostable |
| LTC6993-3 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:TimerBlox: Monostable |
| LTC6993-4 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:TimerBlox: Monostable |
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