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參數(shù)資料
| 型號： | LTC6990CS6#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 9/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC SILICON 1MHZ TSOT23-6 |
| 產品培訓模塊： | TimerBlox Family Timing Devices |
| 特色產品： | TimerBlox? |
| 標準包裝： | 2,500 |
| 系列： | TimerBlox® |
| 類型： | 振蕩器 - 硅 |
| 頻率： | 488Hz ~ 1MHz |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 電流 - 電源： | 235µA |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | SOT-23-6 細型，TSOT-23-6 |
| 包裝： | 帶卷 (TR) |
| 供應商設備封裝： | TSOT-23-6 |
| 安裝類型： | 表面貼裝 |
| 配用： | DC1562A-A-ND - BOARD EVAL LTC6990 |
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LTC6990
17
6990fc
For more information www.linear.com/LTC6990
Figure 12. VCO Transfer Function
VCTRL (V)
1
f OUT
(kHz)
100
80
40
20
60
0
2
6990 F12
4
3
APPLICATIONS INFORMATION
Step 4: Calculate and Select RSET
The final step is to calculate the correct value for RSET
using the following equation:
RSET =
1MHz 50k
NDIV f(0V) VSET KVCO
(
)
(3e)
Select the standard resistor value closest to the calculated
value.
Some applications require combinations of fOUT(MIN),
fOUT(MAX), VCTRL(MIN) and VCTRL(MAX) that are not achiev-
able. These applications result in unrealistic or unrealiz-
able (e.g. negative value) resistors. These applications
will require preconditioning of the VCTRL signal via range
scaling and/or level shifting to place the VCTRL into a range
that yields realistic resistor values.
Frequency Error in VCO Applications Due to VSET Error
As stated earlier, f(0V) represents the frequency for VCTRL
= 0V, which is the same value as would be generated by
a single resistor between SET and GND with a value of
RSET || RVCO. Therefore, f(0V) is not affected by error or
drift in VSET (i.e. VSET adds no frequency error when
VCTRL = 0V).
The accuracy of KVCO does depend on VSET because the
output frequency is controlled by the ratio of VCTRL to
VSET. The frequency error (in Hertz) due to VSET is ap-
proximated by:
fOUT KVCO VCTRL
VSET
As the equation indicates, the potential for error in output
frequency due to VSET error increases with KVCO and is
at its largest when VCTRL is at its maximum. Recall that
when VCTRL is at its maximum, the output frequency is
at its minimum. With the maximum absolute frequency
error (in Hertz) occurring at the lowest output frequency,
the relative frequency error (in percent) can be significant.
VSET is nominally 1.0V with a maximum error of ±30mV
for at most a ±3% error term. However, this ±3% po-
tential error term is multiplied by both VCTRL and KVCO.
Wide frequency range applications (high KVCO) can have
frequency errors greater than ±50% at the highest VCTRL
voltage (lowest fOUT). For this reason the simple, two
resistor VCO circuit must be used with caution for ap-
plications where the frequency range is greater than 4:1.
Restricting the range to 4:1 typically keeps the frequency
error due to VSET variation below 10%.
For wide frequency range applications, the non-inverting
VCO circuit shown in Figure 13 is preferred because the
maximum frequency error occurs when the frequency
is highest, keeping the relative error (in percent) much
smaller.
Example: Design a VCO with the Following Parameters
fOUT(MAX) = 100kHz at VCTRL(MIN) = 1V
fOUT(MIN) = 10kHz at VCTRL(MAX) = 4V
Step 1: Select the NDIV Value
First, choose an NDIV that meets the requirements of
Equation (3a).
6.25 ≤ NDIV ≤ 10
The application’s desired frequency range is 10:1, which
isn’t always possible. However, in this case NDIV=8meets
both requirements of Equation (3).
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