參數(shù)資料
型號(hào)： LTC695ISW-3.3
廠商： LINEAR TECHNOLOGY CORP
元件分類： 電源管理
英文描述： 3.3V Microprocessor Supervisory Circuits
中文描述： 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16
封裝： 0.300 INCH, PLASTIC, SOP-16
文件頁(yè)數(shù)： 12/16頁(yè)
文件大?。?/td> 138K
代理商： LTC695ISW-3.3
12
LTC 694-3.3/LTC 695-3.3
U
S
A
O
PPLICATI
W
U
I FOR ATIO
U
V
3 VR1
.3
R3
850mV
HYSTERESIS
=
=
R3
≈
3.88 R1
Choose R3 = 200k and R1 = 51k. Also select R4 = 10k
which is much smaller than R3.
5V =1.3V 1+R2±(3.3V ±1.3V)51
13 210
k
k
k
R2 = 15.8k, Choose nearest 5% resistor 16k and recalcu-
late V
L
,
V
1.3V 1
16k±(3.3V ±1.3V)51
1.3V(210k
V
1.3V 1
51k
16k
51k
200k
5
V
(4.96V ±3.4V)
100mV/ms
15.6ms
L
H
=
+
=
=
+
+
=
=
496
.
77
.
k
V
V
HYSTERESIS
= 5.77V – 4.96V = 810mV
The 15.6ms allows enough time to execute shutdown
procedure for microprocessor and 810mV of hysteresis
would prevent PFO from going low due to the noise of V
IN
.
Example 2:
The circuit in Figure 9 can be used to measure
the regulated 3.3V supply to provide early warning of
power failure. Because of variations in the PFI threshold,
this circuit requires adjustment to ensure the PFI com-
parator trips before the reset threshold is reached. Adjust
R5 such that the PFO output goes low when the V
CC
supply
reaches the desired level (e.g., 3.1V).
Monitoring the Status of the Battery
C3 can also monitor the status of the memory back-up
battery (Figure 10). If desired, the CE OUT can be used to
apply a test load to the battery. Since CE OUT is forced high
in battery back-up mode, the test load will not be applied
to the battery while it is in use, even if the microprocessor
is not powered.
Watchdog Timer
The LTC694-3.3/LTC695-3.3 provide a watchdog timer
function to monitor the activity of the microprocessor. If
the microprocessor does not toggle the watchdog input
(WDI) within a seleced time-out period, RESET is forced to
active low for a minimum of 140ms. The reset active time
is adjustable on the LTC695-3.3. Since many systems can
not service the watchdog timer immediately after a reset,
the LTC695-3.3 has a longer time-out period (1.0 second
minimum) right after a reset is issued. The normal time-
out period (70ms minimum) becomes effective following
the first transition of WDI after RESET is inactive. The
watchdog time-out period is fixed at 1.0 second minimum
on the LTC694-3.3. Figure 11 shows the timing diagram of
watchdog time-out period and reset active time. The
watchdog time-out period is restarted as soon as RESET
is inactive. When either a high-to-low or low-to-high
transition occurs at the WDI pin prior to time-out, the
watchdog time is reset and begins to time out again. To
ensure the watchdog time does not time out, either a high-
to-low or low-to-high transition on the WDI pin must
occur at or less than the minimum time-out period. If the
input to the WDI pin remains either high or low, reset
pulses will be issued every 1.6 seconds typically. The
watchdog time can be deactivated by floating the WDI pin.
The timer is also disabled when V
CC
falls below the reset
voltage threshold or V
BATT
.
2.4V
3.3V
694/5-3.3 F10
R1
1M
R
L
20k
R2
1.6M
OPTIONAL TEST LOAD
LOW-BATTERY SIGNAL
TO
μ
P I/O PIN
I/O PIN
V
CC
V
BATT
GND
PFI
LTC695-3.3
CE IN
PFO
CE OUT
Figure 10. Back-Up Battery Monitor with Optional Test Load
相關(guān)PDF資料
PDF描述
LTC695CN-3.3 3.3V Microprocessor Supervisory Circuits
LTC695I-3.3 3.3V Microprocessor Supervisory Circuits
LTC695IN-3.3 3.3V Microprocessor Supervisory Circuits
LTC695C-3.3 3.3V Microprocessor Supervisory Circuits
LTC695IN Microprocessor Supervisory Circuits
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