參數(shù)資料
型號(hào)： LTC695CSW-3.3
廠(chǎng)商： LINEAR TECHNOLOGY CORP
元件分類(lèi)： 電源管理
英文描述： 3.3V Microprocessor Supervisory Circuits
中文描述： 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16
封裝： 0.300 INCH, PLASTIC, SOP-16
文件頁(yè)數(shù)： 6/16頁(yè)
文件大?。?/td> 138K
代理商： LTC695CSW-3.3
6
LTC 694-3.3/LTC 695-3.3
PI FU CTIO S
V
CC
:
3.3V Supply Input. The V
CC
pin should be bypassed
with a 0.1
μ
F capacitor.
V
OUT
:
Voltage Output for Backed Up Memory. Bypass with
a capacitor of 0.1
μ
F or greater. During normal operation,
V
OUT
obtains power from V
CC
through an NMOS power
switch, M1, which can deliver up to 50mA and has a typical
on resistance of 5
. When V
CC
is lower than V
BATT
, V
OUT
is internally switched to V
BATT
. If V
OUT
and V
BATT
are not
used, connect V
OUT
to V
CC
.
V
BATT
:
Back-Up Battery Input. When V
CC
falls below V
BATT
,
auxiliary power connected to V
BATT
, is delivered to V
OUT
through PMOS switch, M2. If back-up battery or auxiliary
power is not used, V
BATT
should be connected to GND.
GND:
Ground Pin.
BATT ON:
Battery On Logic Output from Comparator C2.
BATT ON goes low when V
OUT
is internally connected to
V
CC
. The output typically sinks 25mA and can provide base
drive for an external PNP transistor to increase the output
current above the 50mA rating of V
OUT
. BATT ON goes
high when V
OUT
is internally switched to V
BATT
.
PFI:
Power Failure Input. PFI is the noninverting input to
the power-fail comparator, C3. The inverting input is
internally connected to a 1.3V reference. The power failure
output remains high when PFI is above 1.3V and goes low
when PFI is below 1.3V. Connect PFI to GND or V
OUT
when
C3 is not used.
PFO:
Power Failure Output from C3. PFO remains high
when PFI is above 1.3V and goes low when PFI is below
1.3V. When V
CC
is lower than V
BATT
, C3 is shut down and
PFO is forced low.
RESET:
Logic Output for
μ
P Reset Control. Whenever V
CC
falls below either the reset voltage threshold (2.90V,
typically) or V
BATT
, RESET goes active low. After V
CC
returns to 3.3V, the reset pulse generator forces RESET to
remain active low for a minimum of 140ms. When the
watchdog timer is enabled but not serviced prior to a
preset time-out period, the reset pulse generator also
forces RESET to active low for a minimum of 140ms for
every preset time-out period (see Figure 11). The reset
active time is adjustable on the LTC695-3.3. An external
push-button reset can be used in connection with the
RESET output. See Push-Button Reset in Applications
Information section.
RESET:
Active High Logic Ouput. It is the inverse of
RESET.
LOW LINE:
Logic Output from Comparator C1. LOW LINE
indicates a low line condition at the V
CC
input. When V
CC
falls below the reset voltage threshold (2.90V typically),
LOW LINE goes low. As soon as V
CC
rises above the reset
voltage threshold, LOW LINE returns high (see Figure 1).
LOW LINE goes low when V
CC
drops below V
BATT
(see
Table 1).
WDI:
Watchdog Input. WDI is a three-level input. Driving
WDI either high or low for longer than the watchdog time-
out period, forces both RESET and WDO low. Floating WDI
disables the watchdog timer. The timer resets itself with
each transition of the watchdog input (see Figure 11).
WDO:
Watchdog Logic Output. When the watchdog input
remains either high or low for longer than the watchdog
time-out period, WDO goes low. WDO is set high whenever
there is a transition on the WDI pin, or LOW LINE goes low.
The watchdog timer can be disabled by floating WDI (see
Figure 11).
CE IN:
Logic Input to the Chip Enable Gating Circuit. CE IN
can be derived from microprocessor’s address line and/or
decoder output. See Applications Information section and
Figure 5 for additional information.
CE OUT:
Logic Output on the Chip Enable Gating Circuit.
When V
CC
is above the reset voltage threshold, CE OUT is
a buffered replica of CE IN. When V
CC
is below the reset
voltage threshold CE OUT is forced high (see Figure 5).
OSC SEL:
Oscillator Selection Input. When OSC SEL is
high or floating, the internal oscillator sets the reset active
time and watchdog time-out period. Forcing OSC SEL low,
allows OSC IN to be driven from an external clock signal or
an external capacitor can be connected between OSC IN
and GND.
相關(guān)PDF資料
PDF描述
LTC695 Microprocessor Supervisory Circuits
LTC695-3.3 3.3V Microprocessor Supervisory Circuits
LTC695C Microprocessor Supervisory Circuits
LTC695CN Microprocessor Supervisory Circuits
LTC695CSW Microprocessor Supervisory Circuits
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC695CSWPBF 制造商:Linear Technology 功能描述:Processor Supervisor 4.65V 4.65V SOIC16W
LTC695CSW-PBF 制造商:LINER 制造商全稱(chēng):Linear Technology 功能描述:Microprocessor Supervisory Circuits
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LTC695I-3.3 制造商:LINER 制造商全稱(chēng):Linear Technology 功能描述:3.3V Microprocessor Supervisory Circuits
LTC695IN 功能描述:IC MPU SUPERVISORY CIRCUIT 16DIP RoHS:否 類(lèi)別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:開(kāi)路漏極或開(kāi)路集電極 復(fù)位:高有效 復(fù)位超時(shí):- 電壓 - 閥值:1.8V 工作溫度:-40°C ~ 125°C 安裝類(lèi)型:表面貼裝 封裝/外殼:6-TSOP（0.059"，1.50mm 寬）5 引線(xiàn) 供應(yīng)商設(shè)備封裝:5-TSOP 包裝:剪切帶 (CT) 其它名稱(chēng):NCP301HSN18T1GOSCT
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