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參數(shù)資料
| 型號(hào)： | LTC695-3.3 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 3.3V Microprocessor Supervisory Circuits |
| 中文描述： | 3.3微處理器監(jiān)控電路 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 138K |
| 代理商： | LTC695-3.3 |
7
LTC 694-3.3/LTC 695-3.3
OSC IN:
Oscillator Input. OSC IN can be driven by an
external clock signal or an external capacitor can be
connected between OSC IN and GND when OSC SEL is
forced low. In this configuration the nominal reset active
time and watchdog time-out period are determined by the
number of clocks or set by the formula (see Applications
Information section). When OSC SEL is high or floating,
the internal oscillator is enabled and the reset active time
is fixed at 200ms typical for the LTC695-3.3. OSC IN
selects between the 1.6 seconds and 100ms typical
watchdog time-out periods. In both cases, the time-out
period immediately after a reset is 1.6 seconds typical.
W
I
DAGRA
BLOCK
PI FU CTIO S
CHARGE
PUMP
M2
M1
VBATT
VCC
CE IN
PFI
OSC IN
OSC SEL
WDI
RESET PULSE
GENERATOR
WATCHDOG
TIMER
RESET
BATT ON
VOUT
C1
–
1.3V
GND
–
+
+
C2
OSC
TRANSITION
DETECTOR
–
+
C3
WDO
RESET
PFO
LOW LINE
CE OUT
694/5-3.3 BD
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| LTC695C | Microprocessor Supervisory Circuits |
| LTC695CN | Microprocessor Supervisory Circuits |
| LTC695CSW | Microprocessor Supervisory Circuits |
| LTC695I | Microprocessor Supervisory Circuits |
| LTC695ISW | Microprocessor Supervisory Circuits |
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