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參數(shù)資料
| 型號： | LTC6912CGN-1#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PGA DIGITAL R-R DUAL 16SSOP |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 放大器類型： | 可編程增益 |
| 電路數(shù)： | 2 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 26 V/µs |
| 增益帶寬積： | 33MHz |
| 電壓 - 輸入偏移： | 125µV |
| 電流 - 電源： | 2.25mA |
| 電流 - 輸出 / 通道： | 35mA |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 10.5 V，±2.7 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 管件 |
LTC6912
12
6912fa
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: The LTC6912-1C and LTC6912-1I are guaranteed functional over
the operating temperature range of –40
°C to 85°C. The LTC6912-1H is
guaranteed functional over the operating temperature range of –40
°C to
125
°C.
Note 3: The LTC6912-1C is guaranteed to meet specified performance
from 0
°C to 70°C. The LTC6912-1C is designed, characterized and
expected to meet specified performance from – 40
°C to 85°C but is not
tested or QA sampled at these temperatures. The LTC6912-1I is
guaranteed to meet specified performance from –40
°C to 85°C. The
LTC6912-1H is guaranteed to meet specified performance from –40
°C to
125
°C.
Note 4: Output voltage swings are measured as differences between the
output and the respective supply rail.
Note 5: Extended operation with output shorted may cause junction
temperature to exceed the 150
°C limit for GN package and 125°C for a
DFN package is not recommended.
Note 6: Gain is measured with a large signal DC test using an output
excursion between approximately 30% and 70% of supply voltage.
Note 7: Channel-to-channel isolation is measured by applying a 200kHz
input signal to one channel so that its output varies 1VRMS, and measuring
the output voltage RMS of the other channel relative to AGND with its
input tied to AGND. Isolation is calculated:
IsolationB = 20 log
10(VOUTA/VOUTB) or
IsolationA = 20 log10(VOUTB/VOUTA)
High channel-to-channel isolation is strongly dependent on proper circuit
layout. See Applications Information.
Note 8: Offset voltage referred to the INA or INB input is (1 + 1/|GAIN|)
times the offset voltage of the internal op amp, where GAIN is the nominal
gain magnitude. The typical offset voltage values are for 25
°C only. See
Applications Information.
Note 9: Input resistance can vary by approximately
±30% part-to-part at a
given gain setting.
Note 10: Guaranteed by design, not subject to test.
Note 11: States 13, 14 and 15 (binary 11xx) are not used. Programming a
channel to states 8 or higher will configure that particular channel into a
low power shutdown state. In addition, programming a channel into
state 15 (binary 1111) will cause that particular channel to draw up to
20mA of supply current and is not recommended.
U
SERIAL I TERFACE SPECIFICATIO S
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Interface Timing, Dual
±4.5V ~ ±5.5V Supplies (Note 10)
t1
DIN Valid to CLK Setup
●
30
ns
t2
DIN Valid to CLK Hold
●
0ns
t3
CLK High
●
50
ns
t4
CLK Low
●
50
ns
t5
CS/LD Pulse Width
●
40
ns
t6
LSB CLK to CS/LD
●
40
ns
t7
CS/LD Low to CLK
●
20
ns
t8
DOUT Output Delay
CL = 15pF
●
85
ns
t9
CLK Low to CS/LD Low
●
0ns
D3
D2
D31
D0
D3
D7 D4
D3
D4
D2
D31
D0
D3
D7 D4
t5
t8
t9
t7
t6
t1
t2
t4
t3
6912 TD
PREVIOUS BYTE
CURRENT BYTE
CLK
DIN
CS/LD
DOUT
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