參數(shù)資料
型號(hào)： LTC6912CDE-2#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 11/24頁(yè)
文件大?。?/td> 0K
描述： IC PGA DIGITAL R-R DUAL 12-DFN
標(biāo)準(zhǔn)包裝： 2,500
放大器類(lèi)型： 可編程增益
電路數(shù)： 2
輸出類(lèi)型： 滿擺幅
轉(zhuǎn)換速率： 26 V/µs
增益帶寬積： 30MHz
電壓 - 輸入偏移： 125µV
電流 - 電源： 2.25mA
電流 - 輸出 / 通道： 35mA
電壓 - 電源，單路/雙路(±)： 2.7 V ~ 10.5 V，±2.7 V ~ 5.25 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 12-WFDFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 12-DFN-EP（4x3）
包裝： 帶卷 (TR)
LTC6912
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Functional Description
The LTC6912-X is a small outline, wideband, inverting
two-channel amplifier with voltage gains that are indepen-
dently programmable. Each delivers a choice of eight
voltage gains, configurable through a 3-wire serial digital
interface, which accepts TTL or CMOS logic levels (See
Figure 5). Tables 1 and 2 list the nominal gains for the
LTC6912-1 and LTC6912-2 respectively. Gain control
within the amplifier occurs by switching resistors from a
matched array in or out of a closed-loop op amp circuit
using MOS analog switches (Figure 1). The bandwidths of
the individual amplifiers depend on gain setting. The
Typical Performance Characteristics section shows mea-
sured frequency responses.
Description of the 3-Wire SPI Interface
Gain control of each amplifier is independently program-
mable using the 3-wire SPI interface (see Figure 5). Logic
levels for the LTC6912 3-wire serial interface are TTL/
CMOS compatible. When CS/LD is low, the serial data on
DIN is shifted into an 8-bit shift-register on the rising edge
of the clock, with the MSB transferred first. Serial data on
DOUT is shifted out on the clock’s falling edge. A rising edge
on CS/LD will latch the shift-register’s contents into an 8-
bit D-latch and disable the clock internally on the IC. The
upper nibble of the D-latch (4 most significant bits),
configure the gain for the B-channel amplifier. The lower
nibble of the D-latch (4 least significant bits), configures
the gain for the A-channel amplifier. Tables 1 and 2 detail
the nominal gains and respective gain codes. Care must be
taken to ensure CLK is taken low before CS/LD is pulled
low to avoid an extra internal clock pulse to the input of the
8-bit shift-register (See Figure 5).
DOUT is active in all states, therefore DOUT cannot be
“wire-OR’d” to other SPI outputs.
An LTC6912 may be daisy-chained with other LTC6912s
or other devices having serial interfaces by connecting the
DOUT to the DIN of the next chip while CLK and CS/LD
remain common to all chips in the daisy chain. The serial
data is clocked to all the chips then the CS/LD signal is
pulled high to update all of them simultaneously. Figure 6
shows an example of two LTC6912s in a daisy chained SPI
Figure 5. Serial Digital Interface Block Diagram
CLK
CS/LD
SHDN
6912 F05
LOWER NIBBLE UPPER NIBBLE
8-BIT LATCH
8-BIT
SHIFT-REGISTER
CHANNEL A
CHANNEL B
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
DOUT
LSB
MSB
RESET
LE
DIN
OUT A, OUT B: Analog Output. These pins are the output
of the A and B channel amplifiers respectively. Each
operational amplifier can swing rail-to-rail (V+ to V–) as
specified in the Electrical Characteristics table. For best
performance, loading the output as lightly as possible will
minimize signal distortion and gain error. The Electrical
Characteristics table shows performance at output cur-
rents up to 10mA, and the current limits which occur when
the output is shorted midsupply at 2.7V and
±5V supplies.
Output current above 10mA is possible but current-limit-
ing circuitry will begin to affect amplifier performance at
approximately 20mA. Long-term operation above 20mA
output is not recommended. Do not exceed maximum
junction temperature of 150
°C for a GN and 125°C for a
DFN package. The output will drive capacitive loads up to
50pF. Capacitances higher than 50pF should be isolated
by a series resistor (10
or higher).
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