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參數(shù)資料
| 型號(hào)： | LTC6911IMS-2#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PGA DIGITAL R-R DUAL 10MSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 放大器類型： | 可編程增益 |
| 電路數(shù)： | 2 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 16 V/µs |
| 增益帶寬積： | 11MHz |
| 電壓 - 輸入偏移： | 2000µV |
| 電流 - 電源： | 3.1mA |
| 電流 - 輸出 / 通道： | 35mA |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 10.5 V，±2.7 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
LTC6911-1/LTC6911-2
15
sn691112 691112fs
APPLICATIO S I FOR ATIO
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Functional Description
The LTC6911-1/LTC6911-2 are small outline, wideband
inverting 2-channel amplifiers whose voltage gain is digi-
tally programmable. Each delivers a choice of eight volt-
age gains, controlled by the 3-bit digital parallel interface
(G pins), which accept CMOS logic levels. The gain code
is always monotonic; an increase in the 3-bit binary
number (G2 G1 G0) causes an increase in the gain. Tables
1 and 2 list the nominal voltage gains for LTC6911-1 and
LTC6911-2 respectively. Gain control within each ampli-
fier occurs by switching resistors from a matched array in
or out of a closed-loop op amp circuit using MOS analog
switches (Figure 1). Bandwidth depends on gain setting.
Curves in the Typical Performance Characteristics section
show measured frequency responses.
Digital Control
Logic levels for the LTC6911-X digital gain control inputs
(Pins 4, 5, 6) are nominally rail-to-rail CMOS, but can
swing above V+ so long as the positive swing does not
exceed 10.5V with respect to V–. Each logic input has a
small pull-down current source which can sink up to 10
A
and is used to force the part into a gain of “zero” if the logic
inputs are left unconnected. A logic 1 is nominally V+. A
logic 0 is nominally V– or alternatively, 0V when using
±5V
supplies. The parts are tested with the values listed in the
Electrical Characteristics table. Digital Input “High” and
“Low” voltages are 10% and 90% of the nominal full
excursion on the inputs. That is, the tested logic levels are
0.27V and 2.43V with a 2.7V supply, 0.5V and 4.5V with a
5V supply, and 0.5V and 4.5V with
±5V supplies. Do not
attempt to drive the digital inputs with TTL logic levels. TTL
logic sources should be adapted with suitable pull-up
resistors to V+ keeping in mind the internal pull-down
current sources so that for a logic 1 they will swing to the
positive rail.
Timing Constraints
Settling time in the CMOS gain-control logic is typically
several nanoseconds and is faster than the analog signal
path. When amplifier gain changes, the limiting timing is
analog, not digital, because the effects of digital input
changes are observed only through the analog output
(Figure 1). The LTC6911-X’s logic is static (not latched)
and therefore lacks bus timing requirements. However, as
with any programmable-gain amplifier, each gain change
causes an output transient as the amplifier’s output moves,
with finite speed, toward a differently scaled version of the
input signal. Varying the gain faster than the output can
settle produces a garbled output signal. The LTC6911-X
analog path settles with a characteristic time constant or
time scale,
τ, that is roughly the standard value for a first
order band limited response:
τ = 0.35/(2 π f–3dB)
See the –3dB BW vs Gain Setting graph in the Typical
Performance Characteristics.
Offset Voltage vs Gain Setting
The Electrical Characteristics table lists DC gain depen-
dent voltage offset error in two gain configurations. The
voltage offsets listed, VOS(IN), are referred to the input pin
(INA or INB). These offsets are directly related to the
internal amplifier input voltage offset, VOS(OA), by the
magnitude of programmed gain, G:
VV
G
OS OA
OS IN
()
( )
=
+
1
The input referred offset, VOS(IN), for any gain setting can
be inferred from VOS(OA) and the gain magnitude, G. For
example, an internal offset VOS(OA) of 1mV will appear
referred to the INA and INB pins as 2mV at a gain setting
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