V– 6910 F04 OUT
參數(shù)資料
型號(hào)： LTC6910-2HTS8#TRM
廠(chǎng)商： Linear Technology
文件頁(yè)數(shù)： 7/24頁(yè)
文件大?。?/td> 0K
描述： IC PGA DIGITAL R-R I/O TSOT23-8
標(biāo)準(zhǔn)包裝： 1
放大器類(lèi)型： 可編程增益
電路數(shù)： 1
輸出類(lèi)型： 滿(mǎn)擺幅
轉(zhuǎn)換速率： 16 V/µs
增益帶寬積： 13MHz
電壓 - 輸入偏移： 1500µV
電流 - 電源： 3.5mA
電流 - 輸出 / 通道： 35mA
電壓 - 電源，單路/雙路(±)： 2.7 V ~ 10.5 V，±2.7 V ~ 5.25 V
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： SOT-23-8 薄型，TSOT-23-8
供應(yīng)商設(shè)備封裝： TSOT-23-8
包裝： 剪切帶 (CT)
其它名稱(chēng)： LTC6910-2HTS8
LTC6910-2HTS8#TRMCT
LTC6910-2HTS8-ND
LTC6910-1
LTC6910-2/LTC6910-3
15
6910123fa
–
+
INPUT R ARRAY
FEEDBACK R ARRAY
V–
6910 F04
OUT
V+
10k
MOS-INPUT
OP AMP
IN
AGND
10k
2
V–
4
V+
8
G1
G2
G0
1
3
CMOS LOGIC
6
7
5
Figure 4. Block Diagram
UU
U
PI FU CTIO S
Where AGND does not connect to a ground plane, as in
Figures 1 and 3, it is important to AC-bypass the AGND pin.
This is especially true when AGND is used as a reference
voltage for other circuitry. Also, without a bypass capaci-
tor, wideband noise will enter the signal path from the
internal voltage divider resistors that set the DC voltage on
AGND. This noise can reduce SNR by 3dB at high gain
settings. The resistors present a Thévenin equivalent of
approximately 5k to the AGND pin. An external capacitor
from AGND to the ground plane, whose impedance is well
below 5k at frequencies of interest, will suppress this
noise. A 1
Fhighqualitycapacitoriseffectiveinsuppress-
ing resistor noise for frequencies down to 1kHz. Larger
capacitors extend this suppression to proportionately
lower frequencies. This issue does not arise in symmetri-
cal dual supply applications (Figure 2) because AGND
goes directly to ground.
In applications requiring an analog ground reference other
than halfway between the supply rails, the user can over-
ride the built-in analog ground reference by tying the
AGND pin to a reference voltage within the AGND voltage
range specified in the Electrical Characteristics table. The
AGND pin will load the external reference with approxi-
mately 5k returned to the mid-supply potential. AGND
should still be capacitively bypassed to a ground plane as
noted above. Do not connect the AGND pin to the V– pin.
IN (Pin 3): Analog Input. The input signal to the amplifier
in the LTC6910-X is the voltage difference between the IN
and AGND pins. The IN pin connects internally to a digitally
controlled resistance whose other end is a current sum-
ming point at the same potential as the AGND pin (Fig-
ure 4). At unity gain (digital input 001), the value of this
input resistance is approximately 10k
and the IN voltage
range is rail-to-rail (V+ to V–). At gain settings above unity
(digital input 010 or higher), the input resistance falls.
Also, the linear input voltage range falls in inverse propor-
tion to gain. (The higher gains are designed to boost lower
level signals with good noise performance.) Tables 1, 2,
and 3 summarize this behavior. In the “zero” gain state
(digital input 000), analog switches disconnect the IN pin
internally and this pin presents a very high input resis-
tance. The input may vary from rail to rail in the “zero” gain
setting but the output is insensitive to it and remains at the
AGND potential. Circuitry driving the IN pin must consider
the LTC6910-X’s input resistance and the variation of this
resistance when used at multiple gain settings. Signal
sources with significant output resistance may introduce
a gain error as the source’s output resistance and the
LTC6910-X’s input resistance form a voltage divider. This
is especially true at the higher gain settings where the
input resistance is lowest.
In single supply voltage applications at elevated gain
settings (digital input 010 or higher), it is important to
remember that the LTC6910-X’s DC ground reference for
both input and output is AGND, not V–. With increasing
gains, the LTC6910-X’s input voltage range for unclipped
output is no longer rail-to-rail but shrinks toward AGND.
The OUT pin also swings positive or negative with respect
to AGND. At unity gain (digital input 001), both IN and OUT
voltages can swing from rail to rail (Tables 1, 2, 3).
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