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參數(shù)資料
| 型號： | LTC6910-1HTS8#TRMPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PGA DIGITAL R-R I/O TSOT23-8 |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 放大器類型： | 可編程增益 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 16 V/µs |
| 增益帶寬積： | 11MHz |
| 電壓 - 輸入偏移： | 1500µV |
| 電流 - 電源： | 3.5mA |
| 電流 - 輸出 / 通道： | 35mA |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 10.5 V，±2.7 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 薄型，TSOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | TSOT-23-8 |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | LTC6910-1HTS8#PBF LTC6910-1HTS8#PBF-ND |
LTC6910-1
LTC6910-2/LTC6910-3
17
6910123fa
Functional Description
The LTC6910 family are small outline, wideband inverting
DC amplifiers whose voltage gain is digitally program-
mable. Each delivers a choice of eight voltage gains,
controlled by the 3-bit digital inputs to the G pins, which
accept CMOS logic levels. The gain code is always mono-
tonic; an increase in the 3-bit binary number (G2 G1 G0)
causes an increase in the gain. Table 1, Table 2 and Table 3
list the nominal voltage gains for LTC6910-1, LTC6910-2
and LTC6910-3 respectively. Gain control within each
amplifier occurs by switching resistors from a matched
array in or out of a closed-loop op amp circuit using MOS
analog switches (Figure 4). Bandwidth depends on gain
setting. Curves in the Typical Performance Characteristics
section show measured frequency responses.
Digital Control
Logic levels for the LTC6910-X digital gain control inputs
(Pins 5, 6, 7) are nominally rail-to-rail CMOS. Logic 1 is V+,
logic 0 is V– or alternatively 0V when using
±5V supplies.
The part is tested with the values listed in the Electrical
Characteristics table (Digital Input “High” and “Low” Volt-
ages), which are 10% and 90% of full excursion on the
inputs. That is, the tested logic levels are 0.27V and 2.43V
with a 2.7V supply, 0.5V and 4.5V levels with 0V and 5V
supply rails, and 0.5V and 4.5V logic levels at
±5V sup-
plies. Do not attempt to drive the digital inputs with TTL
logic levels (such as HCT or LS logic), which normally do
not swing near +5V. TTL sources should be adapted with
CMOS drivers or suitable pull-up resistors to 5V so that
they will swing to the positive rail.
Timing Constraints
Settling time in the CMOS gain-control logic is typically
several nanoseconds and faster than the analog signal
path. When amplifier gain changes, the limiting timing is
analog, not digital, because the effects of digital input
changes are observed only through the analog output
(Figure 4). The LTC6910-X’s logic is static (not latched)
and therefore lacks bus timing requirements. However, as
with any programmable-gain amplifier, each gain change
causes an output transient as the amplifier’s output moves,
with finite speed, toward a differently scaled version of the
input signal. Varying the gain faster than the output can
settle produces a garbled output signal. The LTC6910-X
analog path settles with a characteristic time constant or
time scale,
τ, that is roughly the standard value for a first
order band limited response:
τ = 1 / (2 π f-3dB),
where f-3dB is the –3dB bandwidth of the amplifier. For
example, when the upper –3dB frequency is 1MHz,
τ is
about 160ns. The bandwidth, and therefore
τ, varies with
gain (see Frequency Response and –3dB Bandwidth curves
in Typical Performance Characteristics). After a gain change
it is the
new gain value that determines the settling time
constant. Exact settling timing depends on the gain change,
the input signal and the possibility of slew limiting at the
output. However as a basic guideline, the range of
τis20ns
to 1400ns for the LTC6910-1, 20ns to 900ns for the
LTC6910-2 and 20ns to 120ns for the LTC6910-3. These
numbers correspond to the ranges of –3dB Bandwidth in
the plots of that title under Typical Performance Character-
istics.
Offset Voltage vs Gain Setting
The electrical tables list DC offset (error) voltage at the
inputs of the internal op-amp in Figure 4, VOS(OA), which
is the source of DC offsets in the LTC6910-X. The tables
also show the resulting, gain dependent offset voltage
referred to the IN pin, VOS(IN). These two measures are
related through the feedback/input resistor ratio, which
equals the nominal gain-magnitude setting, G:
VOS(IN) = (1 + 1/G) VOS(OA)
Offset voltages at any gain setting can be inferred from this
relationship. For example, an internal offset VOS(OA) of
1mV will appear referred to the IN pin as 2mV at a gain
setting G of 1, or 1.5mV at a gain setting of 2. At high gains,
VOS(IN) approaches VOS(OA). (Offset voltage can be of
either polarity; it is a statistical parameter centered on
zero.) The MOS input circuitry of the internal op amp in
Figure 4 draws negligible input currents (unlike some op
amps), so only VOS(OA) and G affect the overall amplifier’s
offset.
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