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參數(shù)資料
| 型號(hào)： | LTC6909IMS#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類(lèi)： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | LEAD FREE, PLASTIC, MSOP-16 |
| 文件頁(yè)數(shù)： | 19/22頁(yè) |
| 文件大小： | 0K |
| 代理商： | LTC6909IMS#TRPBF |
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LTC6909
6
6909fa
V+A (Pin 1): Analog Voltage Supply (2.7V ≤ V+A ≤ 5.5V).
This supply should be kept free of noise and ripple. It
should be bypassed directly to GND with a 0.1F or greater
low ESR capacitor. V+A and V+D must be connected to the
same supply voltage.
GND (Pin 2): Ground Connections. Should be tied to a
ground plane for best performance.
PH0, PH1, PH2 (Pins 3, 4, 15): Output Phasing Selec-
tion Pins. These are standard CMOS logic input pins and
they do not have an internal pull-up or pull-down. These
pins must be connected to a valid logic input 0 or 1 volt-
age. Connect the pins to GND for a logic 0 and to the V+D
pin for a logic 1. These pins configure the output phase
relationships as follows:
PH2
PH1
PH0
MODE
0
All Outputs Are Floating (Hi-Z)
0
1
All Outputs Are Held Low
0
1
0
3-Phase Mode (PH = 3)
0
1
4-Phase Mode (PH = 4)
1
0
5-Phase Mode (PH = 5)
1
0
1
6-Phase Mode (PH = 6)
1
0
7-Phase Mode (PH = 7)
1
8-Phase Mode (PH = 8)
The PH0, PH1, PH2 pin connections not only determine
the phase relationship of the output signals but also divide
the master oscillator frequency by the value PH.
OUT1 Through OUT8 (Pins 5 Through 12): Oscillator
Outputs. These are CMOS rail-to-rail logic outputs with
a series resistance of approximately 40Ω, capable of
driving 1k and/or 50pF loads. Larger loads may cause
minor frequency inaccuracies due to supply bounce at
high frequencies. When any output pin is not in use, it is
in a floating, high impedance state. The outputs are also
held in a high impedance state during start-up. After the
part’s internal frequency setting loop has settled, the out-
puts are active, clean and operating at the set frequency
(first cycle accurate).
V+D (Pin 13): Digital Voltage Supply (2.7V ≤ V+D ≤ 5.5V).
This pin should be bypassed directly to GND with a 0.1F
or greater low ESR capacitor. V+D and V+A must be con-
nected to the same supply voltage.
MOD (Pin 14): Spread Spectrum Frequency Modulation
Setting Input. This input selects among four modulation
rate settings. The MOD pin should be tied to ground for
an fOUT/16 modulation rate. Floating the MOD pin selects
an fOUT/32 modulation rate. The MOD pin should be tied
to V+D for the fOUT/64 modulation rate. Tying one of the
active outputs to the MOD pin turns the modulation off.
To detect a floating MOD pin, the LTC6909 attempts to
pull the pin to the midsupply point. This is realized with
two internal current sources, one tied to V+D and MOD
and the other one tied to GND and MOD. Therefore, driv-
ing the MOD pin high requires sourcing approximately
2A. Likewise, driving the MOD pin low requires sinking
approximately 2A. When the MOD pin is floated for the
fOUT/32 modulation rate, it must be bypassed using a
1nF or larger, capacitor to GND. Any AC signal coupling
to the MOD pin could potentially be detected and stop the
frequency modulation.
SET (Pin 16): Frequency Setting Resistor Input. The value
of the resistor connected between this pin and V+A deter-
mines the frequency of the master oscillator. The output
frequency, fOUT, is the master oscillator frequency divided
by PH as set by the PH0, PH1 and PH2 pin connections.
The voltage on this pin is held approximately 1.1V below
V+A. For best performance, use a precision metal film
resistor with a value between 20k and 400k, and limit the
capacitance on the pin to less than 10pF. Resistor values
outside of this range will have some loss of accuracy as
noted in the Electrical Characteristics table.
pin Functions
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