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參數(shù)資料
| 型號： | LTC6906CS6#TRM |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC SILICON 1MHZ TSOT23-6 |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 類型： | 振蕩器 - 硅 |
| 頻率： | 10kHz ~ 1MHz |
| 電源電壓： | 2.25 V ~ 3.6 V |
| 電流 - 電源： | 78µA |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | SOT-23-6 細(xì)型，TSOT-23-6 |
| 包裝： | 帶卷 (TR) |
| 供應(yīng)商設(shè)備封裝： | TSOT-23-6 |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | LTC6906CS5 LTC6906CS5-ND LTC6906CS6 LTC6906CS6-ND |
LTC6906
5
6906fc
PIN FUNCTIONS
OUT (Pin 1): Oscillator Output. The OUT pin swings from
GND to V+ with an output resistance of approximately
150Ω. For micropower operation, the load resistance must
be kept as high as possible and the load capacitance as
low as possible.
GND (Pin 2): Ground.
DIV (Pin 3): Divider Setting Input. This three-level input
selects one of three internal digital divider settings, de-
termining the value of N in the frequency equation. Tie to
GND for ÷1, leave floating for ÷3 and tie to V+ for ÷10.
When left floating, the LTC6906 pulls Pin 3 to mid-supply
with a 2.5M resistor. When Pin 3 is floating, care should
be taken to reduce coupling from the OUT pin and its
trace to Pin 3. Coupling can be reduced by increasing the
physical space between traces or by shielding the DIV pin
with grounded metal.
SET (Pin 4): Frequency Setting Resistor Input. Connect
a resistor, RSET, from this pin to GND to set the oscillator
frequency. For best performance use a precision metal- or
thin-film resistor of 0.5% or better tolerance and 50ppm/°C
or better temperature coefficient. For lower accuracy ap-
plications, an inexpensive 1% thick-film resistor may be
used. Limit the capacitance in parallel with RSET to less
than 10pF to reduce jitter and to ensure stability. Capaci-
tance greater than 10pF could cause the LTC6906 internal
feedback circuits to oscillate. The voltage on the SET pin
is approximately 650mV and decreases with temperature
by about –2.2mV/°C.
GRD (Pin 5): Guard Signal. This pin can be used to reduce
PC board leakage across the frequency setting resistor,
RSET. The GRD pin is held within a few millivolts of the
SET pin and shunts leakage current away from the SET pin.
To control leakage, connect a bare copper trace (a trace
with no solder mask) to GRD and loop it around the SET
pin and all PC board metal connected to SET.
V+ (Pin 6):
Voltage Supply (2.25V to 3.6V). This supply
is internally decoupled with a 20Ω resistor in series with
an 800pF capacitor. No external decoupling capacitor is
required for OUT pin loads less than 50pF. V+ should be
kept reasonably free of noise and ripple.
BLOCK DIAGRAM
–
+
4
6
1
OP AMP
fOSC
150Ω DRIVER
fOSC
IFB
OUT
6906 BD
3
DIV
PROGRAMMABLE
DIVIDER (n)
(1, 3, 10)
THREE-LEVEL
INPUT
DETECTOR
VOLTAGE
CONTROLLED
OSCILLATOR
(MASTER OSCILLATOR)
fOSC
SET
V+
2
GND
20
800pF
VSET VGRD 650mV
ISET = IFB
FREQUENCY-TO-CURRENT
CONVERTERS
DECOUPLING
NETWORK
BUFFER
GRD
RSET
5M
DIVIDER
SELECT
V+
VSET
5
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