參數(shù)資料
型號: LTC6905MPS5#TR
廠商: LINEAR TECHNOLOGY CORP
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, PDSO5
封裝: PLASTIC, SOT-23, 5 PIN
文件頁數(shù): 10/12頁
文件大?。?/td> 166K
代理商: LTC6905MPS5#TR
LTC6905
7
6905fd
THEORY OF OPERATION
As shown in the Block Diagram, the LTC6905’s master
oscillator is controlled by the ratio of the voltage between
the V+ and SET pins and the current entering the SET pin
(IRES). The voltage on the SET pin is forced to approxi-
mately 1V below V+ by the PMOS transistor and its gate
bias voltage.
A resistor RSET, connected between the V+ and SET pins,
“l(fā)ocks together” the voltage (V+ – VSET) and current, IRES,
variation. This provides the LTC6905’s high precision. The
master oscillation frequency reduces to:
f
MHz
k
R
MHz
MO
SET
=
Ω
+
168 5
10
15
.
To extend the output frequency range, the master oscillator
signal is divided by 1, 2 or 4 before driving OUT (Pin 5).
The LTC6905 is optimized for use with resistors between
10k and 25k, corresponding to oscillator frequencies
between 17.225MHz and 170MHz. The divide-by value is
determined by the state of the DIV input (Pin 4). Tie DIV to
V+ or drive it to within 0.4V of V+ to select ÷1. This is the
highest frequency range, with the master output frequency
passed directly to OUT. The DIV pin may be oated or driven
to midsupply to select ÷2, the intermediate frequency
range. The lowest frequency range, ÷4, is selected by
tying DIV to GND or driving it below 0.5V. Figure 1 shows
the relationship between RSET, divider setting and output
frequency, including the overlapping frequencies.
OUTPUT FREQUENCY (MHz)
10
R
SET
(Ω)
15
20
÷4 ÷2
÷1
6905 F01
10
5
60
110
160
30
25
Figure 1. RSET vs Output Frequency
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