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參數(shù)資料
| 型號(hào)： | LTC6904CMS8 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | 1kHz - 68MHz Serial Port Programmable Oscillator |
| 中文描述： | CRYSTAL OSCILLATOR, CLOCK, 0.001039 MHz - 68 MHz, CMOS OUTPUT |
| 封裝： | PLASTIC, MSOP-8 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 195K |
| 代理商： | LTC6904CMS8 |
LTC6903/LTC6904
10
69034fa
generated by the slave lets the master know that the latest
byte of information was received. The Acknowledge re-
lated clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave-receiver must pull down the SDA
line during the Acknowledge clock pulse so that it remains
a stable LOW during the HIGH period of this clock pulse.
Write Word Protocol
The master initiates communication with the LTC6904
with a START condition and a 7-bit address followed by the
Write Bit (Wr) = 0. The LTC6904 acknowledges and the
master delivers the most significant data byte. Again the
LTC6904 acknowledges and the data is latched into the
most significant data byte input register. The master then
delivers the least significant data byte. The LTC6904
acknowledges once more and latches the data into the
least significant data byte input register. Lastly, the master
terminates the communication with a STOP condition.
Slave Address
The LTC6904 can respond to one of two 7-bit addresses.
The first 6 bits (MSBs) have been factory programmed to
001011. The address pin, ADR (Pin 4) is programmed by
the user and determines the LSB of the slave address, as
shown in the table below:
ADR (Pin 4)
LTC6904 Address
0
0010111
1
0010110
TYPICAL APPLICATIO S
LTC6904 I
2
C Interface
The LTC6904 communicates with a host (master) using
the standard I
2
C 2-wire interface. The Timing Diagram
shows the timing relationship of the signals on the bus.
The two bus lines, SDA and SCL, must be high when the
bus is not in use. External pull-up resistors or current
sources, such as the LTC1694 SMBus Accelerator, are
required on these lines. If the I
2
C interface is not driven
with a standard I
2
C compatible device, care must be taken
to ensure that the SDA line is released during the ACK
cycle to prevent bus contention.
The LTC6904 is a receive-only (slave) device. The master
can communicate with the LTC6904 using the Write Word
protocols as explained later.
Write Word Protocol Used by the LTC6904
Slave Address
A
Wr
MS Data Byte
A
LS Data Byte
A
P
S
7
1
1
8
1
8
6903 AI01
1
1
1
S = Start Condition, Wr = Write Bit = 0, A = Acknowledge, P = Stop Condition
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communi-
cation to a slave device by transmitting a START condi-
tion. A START condition is generated by transitioning SDA
from high to low while SCL is high.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another SMBus device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
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| LTC6904CMS8#PBF | 功能描述:IC OSC SILICON 68MHZ 8-MSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 可編程計(jì)時(shí)器和振蕩器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 類(lèi)型:振蕩器 - 晶體 計(jì)數(shù):- 頻率:- 電源電壓:2.3 V ~ 5.5 V 電流 - 電源:1.07mA 工作溫度:-30°C ~ 80°C 封裝/外殼:SOT-665 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:SS迷你型-5D 安裝類(lèi)型:表面貼裝 其它名稱(chēng):AN8955SSMTXLTR |
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| LTC6904CMS8#TRPBF | 功能描述:IC OSC SILICON 68MHZ 8-MSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 可編程計(jì)時(shí)器和振蕩器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:45 系列:- 類(lèi)型:溫度 - 補(bǔ)償晶體振蕩器（TCXO） 計(jì)數(shù):- 頻率:25MHz 電源電壓:3.135 V ~ 3.465 V 電流 - 電源:1.5mA 工作溫度:-40°C ~ 85°C 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 包裝:管件 供應(yīng)商設(shè)備封裝:16-SOIC W 安裝類(lèi)型:表面貼裝 |
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