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參數(shù)資料
| 型號(hào)： | LTC6900IS5#TRMPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC SILICON 20MHZ TSOT23-5 |
| 產(chǎn)品目錄繪圖： | TSOT23-5 Series Top |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 振蕩器 - 硅 |
| 頻率： | 1kHz ~ 20MHz |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電流 - 電源： | 920µA |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | SOT-23-5 細(xì)型，TSOT-23-5 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 供應(yīng)商設(shè)備封裝： | TSOT-23-5 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 1715 (CN2011-ZH PDF) |
| 其它名稱： | LTC6900IS5#TRMPBFDKR |
LTC6900
8
6900fa
APPLICATIONS INFORMATION
POWER SUPPLY REJECTION
Low Frequency Supply Rejection (Voltage Coefcient)
Figure 5 shows the output frequency sensitivity to power
supply voltage at several different temperatures. The
LTC6900 has a guaranteed voltage coefcient of 0.1%/V
but, as Figure 5 shows, the typical supply sensitivity is
twice as low.
High Frequency Power Supply Rejection
The accuracy of the LTC6900 may be affected when its
power supply generates signicant noise with a frequency
content in the vicinity of the programmed value of fOSC. If a
switching power supply is used to power the LTC6900, and
if the ripple of the power supply is more than 20mV, make
sure the switching frequency and its harmonics are not
related to the output frequency of the LTC6900. Otherwise,
the oscillator may show additional frequency error.
If the LTC6900 is powered by a switching regulator and
the switching frequency or its harmonics coincide with
the output frequency of the LTC6900, the jitter of the
oscillator output may be affected. This phenomenon will
become noticeable if the switching regulator exhibits
ripples beyond 30mV.
START-UP TIME
The start-up time and settling time to within 1% of the
nal value can be estimated by tSTART RSET(3.7μs/kΩ)
+ 10μs. Note the start-up time depends on RSET and it is
independent from the setting of the divider pin. For in-
stance with RSET = 100k, the LTC6900 will settle with 1%
of its 200kHz nal value (N = 10) in approximately 380μs.
Figure 6 shows start-up times for various RSET resistors.
Figure 7 shows an application where a second set resistor
RSET2 is connected in parallel with set resistor RSET1 via
switch S1. When switch S1 is open, the output frequency
of the LTC6900 depends on the value of the resistor RSET1.
When switch S1 is closed, the output frequency of the
LTC6900 depends on the value of the parallel combination
of RSET1 and RSET2.
The start-up time and settling time of the LTC6900 with
switch S1 open (or closed) is described by tSTART shown
above. Once the LTC6900 starts and settles, and switch
S1 closes (or opens), the LTC6900 will settle to its new
output frequency within approximately 70μs.
Jitter
The Peak-to-Peak Jitter vs Output Frequency graph, in the
Typical Performance Characteristics section, shows the
typical clock jitter as a function of oscillator frequency and
power supply voltage. The capacitance from the SET pin,
(Pin 3), to ground must be less than 10pF. If this require-
ment is not met, the jitter will increase.
Figure 5. Supply Sensitivity
Figure 6. Start-Up Time
SUPPLY VOLTAGE (V)
2.5
–0.05
FREQUENCY
DEVIATION
(%)
0
0.05
0.10
0.15
3.0
3.5
4.0
4.5
6900 F05
5.0
5.5
85°C
–40°C
25°C
RSET = 63.2k
PIN 4 = FLOATING (÷10)
TIME AFTER POWER APPLIED (μs)
0
FREQUENCY
ERROR
(%)
20
30
40
600
400k
1000
6900 F06
10
0
–10
200
400
800
50
60
70
63.2k
20k
TA = 25°C
V+ = 5V
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