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| 型號： | LTC6242HVHGN#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OP AMP QUAD R-R 16-SSOP |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 4 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 10 V/µs |
| 增益帶寬積： | 18MHz |
| 電流 - 輸入偏壓： | 0.5pA |
| 電壓 - 輸入偏移： | 60µV |
| 電流 - 電源： | 2.5mA |
| 電流 - 輸出 / 通道： | 35mA |
| 電壓 - 電源，單路/雙路(±)： | 2.8 V ~ 11 V，±1.4 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 管件 |
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LTC6240/LTC6241/LTC6242
22
624012fe
Figure 8. Wideband Difference Amplier with High
Input Impedance and Digitally Programmable Gain
The low bias current and current noise of the LTC6241
allow the use of high valued input resistors, 100k or
greater. Resistors R1, R2, R3 and R4 are equal and the
gain of the difference amplier is one. An LTC6910-2 PGA
amplies the difference amplier output with inverting
gains of –1, –2, –4, –8, –16, –32 and –64. The second
LTC6241 op amp is used as an integrator to set the DC
output voltage equal to the LT6650 reference voltage VREF.
The integrator drives the PGA analog ground to provide
a feedback loop, in addition to blocking any DC voltage
through the PGA. The reference voltage of the LT6650
can be set to a voltage from 400mV to V+ – 350mV with
resistors R5 and R6. If R6 is 20k or less, the error due
to the LT6650 op amp bias current is negligible. The low
voltage offset and drift of the LTC6241 integrator will not
contribute any signicant error to the LT6650 reference
voltage. The LT6650 VREF voltage has a maximum error
of ±2% with 1% resistors. The upper –3dB frequency of
the amplier is set by resistor R3 and capacitor C1 and
is limited by the bandwidth of the PGA when operated at
a gain of 64. Capacitor C2 is equal to C1 and is added to
maintain good common mode rejection at high frequency.
The lower –3dB frequency is set by the integrator resistor
R7, capacitor C3, and the gain setting of the LTC6910-2
PGA. This lower –3dB zero frequency is multiplied by the
PGA gain. The rail-to-rail output of the LTC6910-2 PGA
allows for a maximum output peak-to-peak voltage equal
to twice the VREF voltage. At the maximum gain setting of
64, the maximum peak-to-peak difference between inputs
V1 and V2 is equal to twice VREF divided by 64.
Example Design: Design a programmable gain AC differ-
ence amplier, with a bandwidth of at least 10Hz to 100kHz,
an input impedance equal to or greater than 100kΩ, and
an output DC reference equal to 1V.
a. Select input resistors R1, R2, R3 and R4 equal to
100k.
b. If the upper –3dB frequency is 100kHz then C1 = 1/(2π
R2 f3dB) = 1/(6.28 100kΩ 100kHz) = 15pF (to
the nearest 5% value) and C2 = C1 = 15pF.
c. Select R7 equal to one 1M and set the lower –3dB
frequency to 10Hz at the highest PGA gain of 64, then
C3 = Gain/(2π R7 f3dB) = 64/(6.28 100kΩ 10Hz)
= 1μF. Lower gains settings will give a lower f3dB.
d. Calculate the value of R5 to set the LT6650 reference
equal to 1V;
VREF = 0.4(R5/R6 + 1), so R5 = R6(2.5VREF – 1). For
R6 = 20kΩ, R5 = 30kΩ
With VREF = 1V the maximum input difference voltage
is equal to 2V/64 = 31.2mV.
40nVpp Noise, 0.05μV/°C Drift, Chopped FET
Amplier
Figure 9’s circuit combines the ±5V rail-to-rail performance
of the LTC6241HV with a pair of extremely low noise JFETs
congured in a chopper based carrier modulation scheme
APPLICATIONS INFORMATION
6241 F08
R4
R3
R2
–
+
1/2
LTC6241
C1
C2
1μF
0.1μF
8
765
G2
G1
G0
1
2
234
AGND
OUT
IN
V–
V+
0.1μF
V+
R1
R1 = R2 = R3 = R4
V2
V1
R5
1k
1000pF
3
4
5
R6
20k
LTC6910-2
LT6650
VOUT
VREF
–
+
1/2
LTC6241
C3
R7
100Ω
1μF
DIGITAL INPUTS
G1
G2
GO
GAIN
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
–1
–2
–4
–8
–16
–32
–64
VOUT = (V1 – V2) GAIN + VREF
V
R
Rk
V
REF
=+
=
04
5
6
1
510
5
2
R6 20
.
–
k
d BANDWIDTH
f
RC
HIGH
LOW
HIGH
––
3
1
23
=
12
7
3
f
GAIN
RC
LOW =
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