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參數(shù)資料
| 型號： | LTC6104CMS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 0K |
| 描述： | IC AMP CURRENT SENSE 8-MSOP |
| 標準包裝： | 2,500 |
| 放大器類型： | 電流檢測 |
| 電路數(shù)： | 1 |
| 增益帶寬積： | 200kHz |
| 電流 - 輸入偏壓： | 100nA |
| 電壓 - 輸入偏移： | 85µV |
| 電流 - 電源： | 640µA |
| 電流 - 輸出 / 通道： | 1mA |
| 電壓 - 電源，單路/雙路(±)： | 4 V ~ 60 V，±2 V ~ 30 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
LTC6104
11
6104f
APPLICATIONS INFORMATION
If the maximum output current, IOUT, is limited to 1mA,
ROUT equals 3V/1mA = 3k and RIN = 3k/6 – 0.3Ω (internal
device resistance)
= 499.7Ω.
The output error due to DC offset is ±510V (typ) and
the error due to offset current, IOS, is 3k 100nA =
300V(typ).
The maximum output error can therefore reach ±810V
or 0.027% (–71dB) of the output full scale. Considering
the system input 60dB dynamic range (ISENSE = ±1mA to
±1A), the 71dB performance of the LTC6104 makes this
application feasible.
Output Error, EOUT, Due to the Current Mirror Errors,
IOUT-GAINERR and IOUT-OSERR
When VSENSE is negative, amplier B would be on and
amplier A off. The output of amplier B drives an internal
current mirror which is connected to the OUT pin. This
current mirror has some error associated with it, and this
error can be calculated as follows:
IOUT-GAINERR = ±0.2% IOUT, with IOUT = ±1mA,
IOUT-GAINERR(MAX) = ±2μA
IOUT-OSERR = ±0.2μA
IOUT-ERR(MAX) = IOUT-GAINERR + IOUT-OSERR = ±2μA +
±0.2μA = ±2.2μA
EOUT-ERR(MAX) = IOUT-ERR(MAX) ROUT
The combined effect of amplier offset and current mirror
errors is shown graphically in Figure 4.
Output Error, EOUT, Due to Trace Resistance
The LTC6104 uses the +INB pin for both the positive “B”
amplier input and the positive supply input for both
ampliers. If trace resistance (RT) become signicant
(Figure 5), this supply current can cause an input offset
error, which can be calculated as follows:
ER
I
R
OUT OFFSET
T
S
OUT
IN
()
=
Trace resistances to the –IN terminals will increase the
effective RIN value, causing a gain error (Figure 5). In ad-
dition, internal device resistance will add approximately
0.3
Ω to RIN.
Gain error equals:
A
R
RR
R
V ERROR
OUT
IN
T
OUT
IN
()
.
–
=
++ 03
Minimizing resistance in the input traces is important and
care should be taken in the PCB layout. Make the trace
short and wide. Kelvin connection to the shunt resistor
pad should be used. Avoid tapping into this signal along
Figure 5. Errors from PCB Traces and Other Parasitic Resistances
VSENSE (mV)
0.1
OUTPUT
ERROR
(%)
1
10
100
–500
–100
100
300
0.01
–300
500
6104 F04
MAXIMUM
TYPICAL
RIN = 100
ROUT = 5k
Figure 4. Output Error vs Input Voltage
+
–
8
7
6
4
+INA
OUT
+
–
VS
IS
VS
A
LTC6104
–INA
–INB
RIN
RT
TO
CHARGER/LOAD
RSENSE
VSENSE +
–
+INB
V–
ILOAD
+
CURRENT
MIRROR
+
–
5
B
ROUT
IOUT
VREF
6104 F05
VOUT
+
–
1
RT
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