參數(shù)資料
型號(hào)： LTC6102CDD#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 11/26頁(yè)
文件大?。?/td> 0K
描述： IC AMP CURRENT SENSE 8-DFN
標(biāo)準(zhǔn)包裝： 121
放大器類(lèi)型： 電流檢測(cè)
電路數(shù)： 1
增益帶寬積： 200kHz
電流 - 輸入偏壓： 60pA
電壓 - 輸入偏移： 3µV
電流 - 電源： 420µA
電流 - 輸出 / 通道： 1mA
電壓 - 電源，單路/雙路(±)： 4 V ~ 60 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-WFDFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 8-DFN-EP（3x3）
包裝： 管件
產(chǎn)品目錄頁(yè)面： 1322 (CN2011-ZH PDF)
LTC6102
LTC6102-1/LTC6102HV
19
6102fd
APPLICATIONS INFORMATION
If the output current is very low and an input transient
occurs, there may be a delay before the output voltage
begins changing. This can be reduced by increasing the
minimum output current, either by increasing RSENSE or
decreasing RIN. The effect of increased output current
is illustrated in the step response curves in the Typical
Performance Characteristics section of this datasheet.
Note that the curves are labeled with respect to the initial
output currents.
The speed is also affected by the external circuit. In this
case, if the input changes very quickly, the internal ampli-
er will slew the gate of the internal output FET (Figure 1)
in order to close the internal loop. This results in current
owing through RIN and the internal FET. This current slew
rate will be determined by the amplier and FET charac-
teristics as well as the input resistor, RIN. Using a smaller
RIN will allow the output current to increase more quickly,
decreasing the response time at the output. This will also
have the effect of increasing the maximum output current.
Using a larger ROUT will also decrease the response time,
since VOUT = IOUT ROUT. Reducing RIN and increasing
ROUT will both have the effect of increasing the voltage
gain of the circuit.
Bandwidth
For applications that require higher bandwidth from the
LTC6102, care must be taken in choosing RIN. For a gen-
eral-purpose op-amp, the gain-bandwidth product is used
to determine the speed at a given gain. Gain is determined
by external resistors, and the gain-bandwidth product is
an intrinsic property of the amplier. The same is true
for the LTC6102, except that the feedback resistance is
determined by an internal FET characteristic. The feedback
impedance is approximately 1/gm of the internal MOSFET.
The impedance is reduced as current into –INF is increased.
At 1mA, the impedance of the MOSFET is on the order of
10kΩ. RIN sets the closed-loop gain of the internal loop
as 1/(RIN gm). The bandwidth is then limited to GBW
(RIN gm), with a maximum bandwidth of around 2MHz.
This is illustrated in the characteristic curves, where gain
vs frequency for two input conditions is shown. The exact
impedance of the MOSFET is difcult to determine, as it
is a function of input current, process, and capacitance,
and has a very different characteristic for low currents
vs high currents. However, it is clear that smaller values
of RIN and smaller values of IOUT will generally result in
lower closed-loop bandwidth. VSENSE and RIN should be
chosen to maximize both IOUT and closed-loop gain for
highest speed. Theoretically, maximum bandwidth would
be achieved for the case where VIN = 10VDC and RIN = 10k,
giving IOUT = 1mA and a closed-loop gain near 1. However,
this may not be possible in a practical application. Note
that the MOSFET gm is determined by the average or DC
value of IOUT, not the peak value. Adding DC current to a
small AC input will help increase the bandwidth.
VREG Bypassing
The LTC6102 has an internally regulated supply near V+
for internal bias. It is not intended for use as a supply or
bias pin for external circuitry. A 0.1μF capacitor should be
connected between the VREG and V+ pins. This capacitor
should be located very near to the LTC6102 for the best
performance. In applications which have large supply tran-
sients, a 6.8V zener diode may be used in parallel with this
bypass capacitor for additional transient suppression.
Enable Pin Operation
The LTC6102-1 includes an enable pin which can place
the part into a low power disable state. The enable pin is a
logic input pin referenced to V– and accepts standard TTL
logic levels regardless of the V+ voltage. When the enable
pin is driven high, the part is active. When the enable pin is
oating or pulled low, then the part is disabled and draws
very little supply current. When driven high, the enable pin
draws a few microamps of input bias current.
If there is no external logic supply available, the enable
pin can be pulled to the V+ supply through a large value
resistor. The voltage at the enable pin will be clamped
by the built-in ESD protection structure (which acts like
a zener diode). The resistor should be sized so that the
current through the resistor is a few milliamps or less to
prevent any reduction in long-term reliability. For practi-
cal purposes, the current through the resistor should be
minimized to save power. The resistor value is limited
by the input bias current requirements of the enable
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