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參數(shù)資料
| 型號： | LTC4558EUD#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC20 |
| 封裝： | 3 X 3 MM, 0.75 MM HEIGHT, PLASTIC, QFN-20 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 146K |
| 代理商： | LTC4558EUD#TR |
LTC4558
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Activation/Deactivation
Activation and deactivation sequencing is handled by built-
in circuitry. Each channel may be activated or deactivated
independently of the other. The activation sequence for
each channel is initiated by bringing the ENABLEA,B pin
HIGH. The activation sequence is outlined below:
1. The RSTA,B, CLKA,B and I/OA,B pins are held LOW.
2. VCCA,B is enabled.
3. After VCCA,B is stable at its selected level, the I/OA,B
and RSTA,B channels are enabled.
4. The clock channel is enabled on the rising edge of the
second clock cycle after the I/OA,B pin is enabled.
The deactivation sequence is initiated by bringing the
ENABLEA,B pin LOW. The deactivation sequence is out-
lined below:
1. The reset channel is disabled and RSTA,B is brought
LOW.
2. The clock channel is disabled and the CLKA,B pin is
brought LOW two clock cycles after ENABLEA,B is
brought LOW. If the clock is not running, the clock
channel will be disabled approximately 9μs after the
ENABLEA,B pin is brought LOW.
3. The I/O channel is disabled and the I/OA,B pin is brought
LOW approximately 9μs after the ENABLEA,B pin is
brought LOW.
4. VCCA,B will be depowered after the I/OA,B pin is brought
LOW.
The activation or deactivation sequences will take place
every time a card channel is enabled or disabled. When
a channel is deselected using the CSEL pin, the RSTA,B
state is latched, the I/OA,B channel becomes high imped-
ance and CLKA,B is brought LOW after a maximum of two
clock cycles.
Fault Detection
The VCCA,B, I/OA,B, RSTA,B, CLKA,B and DATA pins are all
protected against short-circuit faults. While there are no
logic outputs to indicate that a fault has occurred, these
pins will be able to tolerate the fault condition until it has
been removed.
The VCCA,B, I/OA,B, and RSTA,B pins possess fault protec-
tion circuitry which will limit the current available to the
pins. Each VCC pin is capable of supplying approximately
90mA (typ) before the output voltage is reduced.
The CLKA,B pins are designed to tolerate faults by reducing
the current drive capability of their output stages. After a
fault is detected by the internal fault detection logic, the
logic waits for a fault detection delay to elapse before
reducing the current drive capability of the output stage.
The reduced current drive allows the LTC4558 to detect
when the fault has been removed.
OPERATION
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