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參數(shù)資料
| 型號： | LTC4425IDD#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO12 |
| 封裝： | 3 X 3 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, DFN-12 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 239K |
| 代理商： | LTC4425IDD#TRPBF |
LTC4425
4
4425f
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The current limit features of this part are intended to protect the
IC from short term or intermittent fault conditions. Continuous operation
above the maximum specied pin current rating may result in device
degradation or failure.
Note 3: Failure to solder the exposed backside of the package to the PC
board ground plane will result in a thermal resistance much greater than
43°C/W on the DD package and greater than 35°C/W on MSE package.
Note 4: The LTC4425E (E grade) is guaranteed to meet specications
from 0°C to 85°C junction temperature. Specications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC4425I (I grade) is guaranteed over the full –40°C to 125°C operating
junction temperature range. The junction temperature, TJ, is calculated
from the ambient temperature, TA, and power dissipation, PD, according to
the formula:
TJ = TA + (PD θJA °C/W).
Note that the maximum ambient temperature is determined by specic
operating conditions in conjunction with board layout, the rated thermal
package thermal resistance and other environmental factors.
Note 5: VIN to VOUT charge current is reduced by thermal foldback as
junction temperature approaches 105°C.
ELECTRICAL CHARACTERISTICS The l denotes the specications which apply over the full operating
junction temperature range, otherwise specications are at TA = 25°C, VIN = 3.8V. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Leakage Balancer
VMID
VMID Output Voltage
VOUT = 3.6V
1.76
1.8
1.84
V
VMID Maximum Current Sourcing Capability
VMID < VOUT/2, VMID < VCLAMP
0.7
mA
VMID Maximum Current Sinking Capability
VMID > VOUT/2, VMID < VCLAMP
1.2
mA
PFO, PFI_RET, PFI
Output Low Voltage (PFO, PFI_RET)
IPIN = 5mA
65
mV
Pin Leakage Current (PFO, PFI_RET)
VPIN = 5V, EN = 0
1
μA
FB Threshold Voltage for Power Good (Rising)
LDO Mode
l
1.09
1.11
1.13
V
Input-to-Output Differential for Power Good (Rising) Normal Mode
265
mV
VPFI
PFI Threshold (Falling)
l
1.18
1.2
1.22
V
PFI Hysteresis
10
mV
IPFI
PFI Pin Input Leakage
100
nA
Power Good Timer Delay
200
ms
Logic Inputs (EN, SEL)
VIL
Logic Low Input Voltage
l
0.4
V
VIH
Logic High Input Voltage
l
1.2
V
IIH
Input Current High
EN, SEL Pins at 5.5V
–1
1
μA
IIL
Input Current Low
EN, SEL Pins at GND
–1
1
μA
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