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參數(shù)資料
| 型號： | LTC4350IGN#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 240K |
| 描述： | IC CTLR HOTSWAP LOADSHARE 16SSOP |
| 標準包裝： | 100 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內(nèi)部開關： | 無 |
| 電源電壓： | 17V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1338 (CN2011-ZH PDF) |
LTC4350
4350fb
pin FuncTions
GND (Pin 8): Chip Ground.
FB (Pin 9): Analog Error Amplifier Input (E/A1). This pin is
used to monitor the output supply voltage with an external
resistive divider. The FB pin voltage is compared to 1.220V
reference. The difference between the FB pin voltage and
the reference is amplified and output on the COMP1 pin.
R
SET
(Pin 10): Analog Output Pin. The I
OUT
amplifier
converts the voltage at the COMP2 pin (down a diode
voltage) to the R
SET
pin. Therefore, the current through
the external resistor (R
SET
) placed between the R
SET
pin
and ground is (COMP2 V
DIODE
)/R
SET
. This current is
used to adjust the output voltage.
I
OUT
(Pin 11): Analog Output Pin. The current flowing into
the I
OUT
pin is equal to the current flowing out of the R
SET
pin that was set by the external resistor R
SET
. This current
is used to adjust the output supply voltage by modifying
the voltage sensed by the power supplys internal voltage
feedback circuitry.
R
(Pin 12): Analog Input Pin. With a sense resistor placed
in the supply path between the R
+
and R
pins, the power
supply current is measured as a voltage drop between R
+
and R
. This voltage is measured by the I
SENSE
block and
multiplied at the GAIN pin.
R
+
(Pin 13): Analog Input Pin. With a sense resistor placed
in the supply path between the R
+
and R
pins, the power
supply current is measured as a voltage drop between R
+
and R
. This voltage is measured by the I
SENSE
block and
multiplied at the GAIN pin.
GATE (Pin14): The high side gate drive for the external
N-Channel power FET . An internal charge pump provides
the gate drive necessary to drive the FETs. The slope of
the voltage rise or fall at the GATE is set by an external
capacitor connected between GATE and GND, and the
10礎 charge pump output current. When the undervoltage
lockout circuit monitoring V
CC
trips, the OV pin is pulled
high or the UV pin is pulled low, the GATE pin is immedi-
ately pulled to GND.
STATUS (Pin 15): Open-Drain Digital Output. The STATUS
pin has an open-drain output to GND. This pin is pulled
low to indicate a fault has occurred in the system. There
are three types of faults. The first is a undervoltage lockout
on V
CC
or the UV pin is low while the output voltage is
active. The second is when the COMP2 pin is above 1.5V
or below 0.5V and the voltage on the GAIN pin is greater
than 100mV . The final failure is when the OV pin is high.
The three faults will activate the pull-down on the STATUS
pin after a timing cycle.
V
CC
(Pin 16): The Positive Supply Input, Ranging from
3.3V to 12V for Normal Operation. I
CC
is typically 1.6mA.
An undervoltage lockout circuit disables the chip until
the voltage at V
CC
is greater than 2.47V . A 0.1礔 bypass
capacitor is required on the V
CC
pin. If the V
CC
pin is tied
to the same power supply output that is being adjusted,
then a 51?decoupling resistor is needed to hold up the
supply during a short to ground on the supply output.
V
CC
must be greater than or equal to the supply that is
connected to the R
+
and R
pins.
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