參數(shù)資料
型號(hào): LTC4313CDD-3#TRPBF
廠商: Linear Technology
文件頁數(shù): 14/20頁
文件大?。?/td> 0K
描述: IC 2WIRE BUS BUFFER 8DFN
標(biāo)準(zhǔn)包裝: 2,500
類型: 2線總線緩沖器
Tx/Rx類型: I²C Logic
電容 - 輸入: 10pF
電源電壓: 2.9 V ~ 5.5 V
電流 - 電源: 8.1mA
安裝類型: 表面貼裝
封裝/外殼: 8-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 8-DFN(3x3)
包裝: 帶卷 (TR)
LTC4313-1/LTC4313-2/
LTC4313-3
3
4313123f
elecTrical characTerisTics
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply/Start-Up
VCC
Input Supply Voltage
l
2.9
5.5
V
VDD,BUS
2-Wire Bus Supply Voltage
LTC4313-1, LTC4313-2
l
2.9
5.5
V
LTC4313-3
l
1.4
5.5
V
ICC
Input Supply Current
VENABLE = VCC = 5.5V, VSDAIN,SCLIN = 0V
(Note 3)
l
6
8.1
10
mA
ICC(DISABLED)
Input Supply Current
VENABLE = 0V, VCC = 5.5V,
VSDAIN,SCLIN = 0V
l
2.5
3.5
4.5
mA
VTH_UVLO
VCC UVLO Threshold
VCC Rising
l
2.55
2.7
2.85
V
VCC_UVLO(HYST) UVLO Threshold Hysteresis Voltage
200
mV
VPRE
Precharge Voltage
SDA, SCL Pins Open
l
0.8
1
1.2
V
Buffers
VOS(SAT)
Buffer Offset Voltage
IOL = 4mA, Driven VSDA,SCL = 50mV
l
100
190
280
mV
IOL = 500A, Driven VSDA,SCL = 50mV
l
15
60
120
mV
VOS
Buffer Offset Voltage
IOL = 4mA, Driven VSDA,SCL = 200mV
l
50
120
180
mV
IOL = 500A, Driven VSDA,SCL = 200mV
l
15
60
115
mV
VIL, FALLING
Buffer Input Logic Low Voltage
VCC = 2.9V, 3.3V, 5.5V
l
0.3VCC 0.33VCC 0.36VCC
V
VIL(HYST)
VIL Hysteresis Voltage
50
mV
ILEAK
Input Leakage Current
SDA, SCL Pins = 5.5V, VCC = 5.5V, 0V
l
±10
A
CIN
Input Capacitance
SDA, SCL Pins (Note 4)
l
10
pF
Rise Time Accelerators (LTC4313-1 and LTC4313-2 Only)
dV/dt(RTA)
Minimum Slew Rate Requirement
SDA, SCL Pins, VCC = 5V
l
0.1
0.2
0.4
V/s
VRTA(TH)
Rise Time Accelerator DC Threshold Voltage VCC = 5V
l
0.38 VCC 0.41VCC 0.44VCC
V
VACC
Buffers Off to Accelerator On Voltage
SDA, SCL Pins, VCC = 5V
l
0.05VCC 0.07VCC
mV
IRTA
Rise Time Accelerator Pull-Up Current
SDA, SCL Pins, VCC = 5V (Note 5)
LTC4313-1
l
15
25
40
mA
LTC4313-2
l
1.5
2.5
3.5
mA
Enable/Control
VEN(TH)
ENABLE Threshold Voltage
l
1
1.4
1.8
V
ILEAK
ENABLE Leakage Current
VENABLE = 5.5V
l
0.1
±10
A
VREADY(OL)
READY Output Low Voltage
IREADY = 3mA, VCC = 5V
l
0.4
V
IREADY(OH)
READY Off Leakage Current
VCC = VREADY = 5V
l
0.1
±5
A
Stuck Low Timeout Circuitry
tTIMEOUT
Bus Stuck Low Timer
l
35
45
55
ms
I2C Interface Timing
fSCL(MAX)
I2C Frequency Max
l
400
kHz
tPDHL
SCL, SDA Fall Delay
VCC = VDD,BUS = 5V, CBUS = 100pF,
RBUS = 10kΩ (Note 4)
130
250
ns
tf
SCL, SDA Fall Times
VCC = VDD,BUS = 5V, CBUS = 100pF,
RBUS = 10kΩ (Note 4)
20
300
ns
tIDLE
Bus Idle Time
l
55
95
175
s
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive and all voltages are referenced to
GND unless otherwise indicated.
Note 3: Test performed with SDA, SCL buffers active.
Note 4: Guaranteed by design and not tested.
Note 5: Measured in a special DC mode with VSDA,SCL = VRTA(TH) + 1V.
The transient IRTA during rising edges for the LTC4313-1 will depend on
the bus loading condition and the slew rate of the bus. The LTC4313-1’s
internal slew rate control circuitry limits the maximum bus rise rate to
75V/s by controlling the transient IRTA.
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