2 = –13kΩ 400pF In 2.1V + 0.15V – 3.3V – 13kΩ2.5mA 0.9V –" />

        參數(shù)資料
        型號: LTC4311CSC6#TRPBF
        廠商: Linear Technology
        文件頁數(shù): 2/12頁
        文件大?。?/td> 0K
        描述: IC ACCELERATOR SMBUS DL SC70-6
        產(chǎn)品培訓模塊: LTC4310 - Hot-Swappable I²C Isolators
        標準包裝: 2,500
        類型: SMBus 加速器
        Tx/Rx類型: I²C Logic
        電源電壓: 1.6 V ~ 5.5 V
        電流 - 電源: 300µA
        安裝類型: 表面貼裝
        封裝/外殼: 6-TSSOP,SC-88,SOT-363
        供應(yīng)商設(shè)備封裝: SC-70-6
        包裝: 帶卷 (TR)
        LTC4311
        10
        4311fa
        APPLICATIONS INFORMATION
        t
        2 = –13kΩ 400pF
        In
        2.1V
        + 0.15V – 3.3V – 13kΩ2.5mA
        0.9V – 3.3V – 13k
        Ω2.5mA
        = 0.205s
        (20)
        t
        r = t1 + t2 = 0.515s + 0.205s = 0.72s
        (21)
        t
        f = 293Ω 400pF
        In
        2.1V
        + 0.15V
        3.3V
        (13k
        Ω+ 300Ω)– 300Ω
        0.8V – 0.15V
        3.3V
        (13k
        Ω+ 300Ω)– 300Ω
        = 0.156s
        (22)
        The rise time meets the 1μs SMBus requirement and the
        fall time meets the 0.3μs requirement. The VOL is satised
        while meeting the minimum slew rate requirements, so RP
        is chosen to be 13kΩ. If the rise time was not met due to
        a large t1, equation 6 can be used to calculate a maximum
        value of RP that will meet the rise time requirements.
        ACK Data Setup Time
        Care must be taken in selecting the value of RS (in series
        with the pull-down driver) to ensure that the data setup
        time requirement for ACK (acknowledge) is fullled. An
        acknowledge is the host releasing the SDA line (pulling
        high) at the end of the last bit sent and the slave device
        pulling the SDA line low before the rising edge of the ACK
        clock pulse.
        The LTC4311 5mA pull-up current is activated when the
        host releases the SDA line, allowing the voltage to rise
        above the LTC4311’s comparator threshold (VTHR). If
        a slave device has a high value of RS, a longer time is
        required for the slave device to pull SDA low before the
        rising edge of the ACK clock pulse. To ensure sufcient
        data setup time for ACK, slave devices with high values
        of RS should pull the SDA low earlier.
        An alternative is the slave device can hold the SCL line low
        until the SDA line reaches a stable state. Then, SCL can
        be released to generate the ACK clock pulse.
        Multiple LTC4311s in Parallel
        In very heavily loaded systems, stronger pull up current
        may be desired. Two LTC4311’s may be used in parallel
        to increase the total pull up current to meet rise time
        requirements.
        Notes on Using the LTC4311 in LTC1694 Applications
        Although the LTC1694 and LTC4311 are functionally similar
        accelerators for I2C, SMBus, and other comparable open
        drain/collector bus applications, the LTC4311 offers a lower
        power, higher performance solution in a smaller package
        as compared to the LTC1694. These and other differences
        are listed in Table 1 and must be accounted for if using
        the LTC4311 in LTC1694 applications.
        Table 1. Differences Between LTC1694 and LTC4311
        SPECIFICATION
        LTC1694
        LTC4311
        COMMENTS
        Enable Pin (typ)
        N/A
        1V
        Allows the LTC4311 to be Disabled, Consuming Less than 5μA
        VCC
        2.7V – 6V
        1.6V – 5.5V
        Lower Operating Supply Voltage for Low Voltage Systems
        ICC (typ), BUS1, BUS2 High
        60μA
        26μA
        Lower Standby Current to Conserve Power
        VTHRES (typ)
        0.65V
        Dependent on VCC
        Tighter, Higher Noise Margins and Improved Rise Times
        IPULL-UP (typ)
        2.2mA
        5mA
        Stronger Slew-Limited Source Current for Slewing Higher Bus Capacitances
        fMAX
        100kHz
        400kHz
        Higher Operating Frequency for I2C’s Fast Mode Bus Specication
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