參數(shù)資料
型號: LTC4308IMS8#TRPBF
廠商: Linear Technology
文件頁數(shù): 11/16頁
文件大?。?/td> 168K
描述: IC BUS BUFFER LV 8-MSOP
產(chǎn)品培訓(xùn)模塊: LTC4310 - Hot-Swappable I²C Isolators
標(biāo)準(zhǔn)包裝: 2,500
類型: 熱交換開關(guān)
應(yīng)用: 通用型緩沖器/總線擴(kuò)展器
內(nèi)部開關(guān):
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-MSOP
包裝: 帶卷 (TR)
LTC4308
11
4308f
 APPLICATIONS INFORMATION
Resistor Pull-Up Value Selection
To guarantee the SDAOUT and SCLOUT rise time accelera-
tors are activated during a rising edge, the bus must rise
on its own with a positive slew rate of at least 0.8V/約. To
achieve this, choose a maximum resistor value R
PULLUP
 
using the formula:
    
R
PULLUP
d
(V
BUS(MIN)
0.8V)"1250ns / V
C
BUS
Where R
PULLUP
 is the pull-up resistor value in k? V
BUS(MIN)
 
is the minimum bus pull-up supply voltage and C
BUS
 is
the equivalent bus capacitance in pF .
To estimate the value of C
BUS
, use a general rule of 20pF
of capacitance per device on the bus (10pF for the device
and 10pF for interconnect).
In addition, R
PULLUP
 must be strong enough to overcome
the precharge voltage and provide logic highs on SDAOUT
and SCLOUT for the start-up and connection circuitry to
connect the backplane to the card. To meet this require-
ment, always choose
 
 
 
R
PULLUP
d75k
V
BUS(MIN)
 V
THR(MAX)
V
THR(MAX)
1V
where V
THR(MAX)
 is the maximum speci ed Logic Input
Threshold Voltage, V
THR
.
Further, on SDAIN and SCLIN and for heavily loaded
systems on SDAOUT and SCLOUT , where the selected
R
PULLUP
 value causes the bus to rise at a rate slower than
0.8V/約, users must also guarantee
 
 
R
PULLUP
d
V
BUS(MIN)
 V
THR(MAX)
100糀
 
Live Insertion and Capacitance Buffering Application
Figure 4 and 5 illustrate applications of the LTC4308 that
take advantage of the LTC4308s Hot Swap", capacitance
buffering and output pin precharge features. If the I/O
cards were plugged directly into the backplane without the
LTC4308 buffer, all of the backplane and card capacitances
would add directly together, making rise time and fall time
requirements dif cult to meet. Placing an LTC4308 on the
edge of each card isolates the card capacitance from the
backplane. For a given I/O card, the LTC4308 drives the
capacitance of everything on the card and the backplane
must drive only the capacitance of the LTC4308, which
is less than 10pF .
Figure 4 shows the LTC4308 used in the typical staggered
connector application, where V
CC
 and GND are the longest
early power pins. The early power pins ensure the
LTC4308 is initially powered and forcing the 1V precharge
voltage on the medium length SDA and SCL output pins
before they contact with the backplane busses. Coupled
with ENABLE as the shortest pin, passively pulled to ground
by a resistor, the staggered approach provides additional
time for transients associated with live insertion to settle
before the LTC4308 can be enabled.
Figure 5 shows the LTC4308 in an application where all
of the pins have the same length. In this application, a
resistor is used to hold the ENABLE pin low during live
insertion, until the backplane control circuitry can enable
the device.
Level Shifting Applications
Systems requiring different supply voltages for the
backplane side and the card side can use the LTC4308
for bidirectional level shifting, as shown in Figures 4, 5,
and 7. The LTC4308 can level shift between bus pull-up
supplies as low as 0.9V to as high as 5.5V . Level shifting
allows newer designs that require lower voltage supplies,
such as EEPROMs and microcontrollers, the capability to
interface with legacy backplanes which may be operating
at higher supply voltages.
The LTC4308s negative offset voltage from output to
input allow level shifting applications with high SDAOUT
and SCLOUT V
OL
 to effectively translate to the low voltage
SDAIN and SCLIN busses. Figure 7 shows an application
where 200?resistors, used to provide additional ESD
protection for the Temperature Sensors internal low
impedance pull-down device, generate high V
OL
 on the
SDAOUT and SCLOUT busses.
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