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參數(shù)資料
| 型號： | LTC4305IDHD#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUFFER BUS 2WR ADDRESS 16-DFN |
| 產(chǎn)品培訓(xùn)模塊： | LTC4310 - Hot-Swappable I²C Isolators |
| 標(biāo)準(zhǔn)包裝： | 73 |
| 應(yīng)用： | 帶放大器的多路復(fù)用器 |
| 接口： | SMBus（2 線/I²C） |
| 電源電壓： | 2.2 V ~ 5.5 V |
| 封裝/外殼： | 16-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-DFN（5x4） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
LTC4305
4305f
4
The
● denotes specifications which apply over the full specified temperature
range, otherwise specifications are at TA = 25°C. VCC = 3.3V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Guaranteed by design and not subject to test, unless stated
otherwise in the Conditions.
Note 3: The boosted pull-up currents are regulated to prevent excessively
fast edges for light loads. See the Typical Performance Characteristics for
rise time as a function of VCC and parasitic bus capacitance CBUS and for
IBOOST as a function of VCC and temperature.
Note 4: When a logic low voltage VLOW is forced on one side of the
upstream-downstream buffers, the voltage on the other side is regulated
to a voltage VLOW2 = VLOW + VOS is a positive offset voltage. VOS,DOWN-BUF
is the offset voltage when the LTC4305 is driving the upstream pin (e.g.,
SDAIN) and VOS,DOWN-BUF is the offset voltage when the LTC4305 is
driving the downstream pin (e.g., SDA1). See the Typical Performance
Characteristics for VOS,UP-BUF and VOS,DOWN-BUF as a function of VCC and
bus pull-up current.
Note 5: When floating, the ADR0–ADR2 pins can tolerate pin leakage
currents up to IADR,FLOAT and still convert the address correctly.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I2C Interface
VADR(H)
ADR0–2 Input High Voltage
●
0.75
VCC 0.9 VCC
V
VADR(L)
ADR0–2 Input Low Voltage
●
0.1
VCC 0.25 VCC
V
IADR(IN, L)
ADR0–2 Logic Low Input Current
ADR0–2 = 0V, VCC = 5.5V
●
–30
–60
–80
A
IADR(IN, H)
ADR0–2 Logic High Input Current
ADR0–2 = VCC = 5.5V
●
30
60
80
A
IADR,FLOAT
ADR0–2 Allowed Input Current
VCC = 2.7V, 5.5V (Note 5)
●
±5
±13
A
VSDAIN,SCLIN(TH)
SDAIN, SCLIN Input Falling Threshold Voltages
VCC = 5.5V
●
1.4
1.6
1.8
V
VSDAIN,SCLIN(HY)
SDAIN, SCLIN Hysteresis
30
mV
ISDAIN,SCLIN(OH)
SDAIN, SCLIN Input Current
SCL, SDA = VCC
●
±5
A
CIN
SDA, SCL Input Capacitance
(Note 2)
6
10
pF
VSDAIN(OL)
SDAIN Output Low Voltage
ISDA = 4mA, VCC = 2.7V
●
0.2
0.4
V
I2C Interface Timing
fSCL
Maximum SCL Clock Frequency
(Note 2)
400
kHz
tBUF
Bus Free Time Between Stop/Start Condition
(Note 2)
0.75
1.3
s
tHD, STA
Hold Time After (Repeated) Start Condition
(Note 2)
45
100
ns
tSU, STA
Repeated Start Condition Set-Up Time
(Note 2)
–30
0
ns
tSU, STO
Stop Condition Set-Up Time
(Note 2)
–30
0
ns
tHD, DATI
Data Hold Time Input
(Note 2)
–25
0
ns
tHD, DATO
Data Hold Time Output
(Note 2)
300
600
900
ns
tSU, DAT
Data Set-Up Time
(Note 2)
50
100
ns
tf
SCL, SDA Fall Times
(Note 2)
20 + 0.1
300
ns
CBUS
tSP
Pulse Width of Spikes Suppressed by the
(Note 2)
50
150
250
ns
Input Filter
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