參數(shù)資料
型號(hào): LTC4300A-1
廠商: Linear Technology Corporation
英文描述: Hot Swappable 2-Wire Bus Buffers
中文描述: 熱插拔2線總線緩沖器
文件頁數(shù): 3/16頁
文件大小: 291K
代理商: LTC4300A-1
LTC4300A-1/LTC4300A-2
3
sn4300a12 4300a12fs
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired
Note 2:
I
PULLUPAC
varies with temperature and V
CC
voltage, as shown in
the Typical Performance Characteristics section.
Note 3:
The connection circuitry always regulates its output to a higher
voltage than its input. The magnitude of this offset voltage as a function of
the pullup resistor and V
CC
voltage is shown in the Typical Performance
Characteristics section.
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specfications are at T
A
= 25
°
C. V
CC
= 2.7V to 5.5V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
Rise-Time Accelerators
I
PULLUPAC
Transient Boosted Pull-Up Current
Positive Transition on SDA,SCL, V
CC
= 2.7V,
Slew Rate = 1.25V/
μ
s (Note 2),
LTC4300A-2, ACC = 0.7 V
CC2
, V
CC2
= 2.7V
V
ACCDIS
Accelerator Disable Threshold
LTC4300A-2
V
ACCEN
Accelerator Enable Threshold
LTC4300A-2
I
VACC
ACC Input Current
LTC4300A-2
t
PDOFF
ACC Delay, On/Off
LTC4300A-2
Input-Output Connection
V
OS
Input-Output Offset Voltage
10k to V
CC
on SDA, SCL, V
CC
= 3.3V (Note 3),
LTC4300A-2, V
CC2
= 3.3V, V
IN
= 0.2V
f
SCL, SDA
Operating Frequency
Guaranteed by Design, Not Subject to Test
C
IN
Digital Input Capacitance
Guaranteed by Design, Not Subject to Test
V
OL
Output Low Voltage, Input = 0V
SDA, SCL Pins, I
SINK
= 3mA, V
CC
= 2.7V,
V
CC2
= 2.7V, LTC4300A-2
I
LEAK
Input Leakage Current
SDA, SCL Pins = V
CC
= 5.5V,
LTC4300A-2, V
CC2
= 5.5V
Timing Characteristics
f
I2C
(Note 4)
t
BUF
Bus Free Time Between Stop
(Note 4)
and Start Condition
t
hD,STA
Hold Time After (Repeated)
(Note 4)
Start Condition
t
su,STA
Repeated Start Condition Setup Time
(Note 4)
t
su,STO
Stop Condition Setup Time
(Note 4)
t
hD, DAT
Data Hold Time
(Note 4)
t
su, DAT
Data Setup Time
(Note 4)
t
LOW
Clock Low Period
(Note 4)
t
HIGH
Clock High Period
(Note 4)
t
f
Clock, Data Fall Time
(Notes 4, 5)
t
r
Clock, Data Rise Time
(Notes 4, 5)
The
G
denotes the specifications which apply over the full operating
MIN
TYP
MAX
UNITS
1
2
mA
0.3 V
CC2
0.5 V
CC2
0.5 V
CC2
±
0.1
5
V
V
0.7 V
CC2
±
1
μ
A
ns
G
0
100
175
mV
0
400
10
0.4
kHz
pF
G
0
V
±
5
μ
A
I
2
C Operating Frequency
0
400
kHz
μ
s
1.3
0.6
μ
s
0.6
0.6
300
100
1.3
0.6
μ
s
μ
s
ns
ns
μ
s
μ
s
ns
ns
20 + 0.1 C
B
20 + 0.1 C
B
300
300
Note 4:
Guaranteed by design, not subject to test.
Note 5:
C
B
= total capacitance of one bus line in pF.
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