參數(shù)資料
型號: LTC4259ACGW
廠商: LINEAR TECHNOLOGY CORP
元件分類: 電源管理
英文描述: Quad IEEE 802.3af Power over Ethernet Controller with AC Disconnect
中文描述: 4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO36
封裝: 0.300 INCH, PLASTIC, SSOP-36
文件頁數(shù): 23/32頁
文件大?。?/td> 326K
代理商: LTC4259ACGW
LTC4259A
23
4259Af
APPLICATIOU
W
U
U
SERIAL DIGITAL INTERFACE
The LTC4259A communicates with a host (master) using
the standard 2-wire interface as described in the SMBus
Specification Version 2.0 (available at http://smbus.org).
The SMBus is an extension of the I
2
C bus, and the
LTC4259A is also compatible with the I
2
C bus standard.
The Timing Diagrams (Figures 6 through 10) show the
timing relationship of the signals on the bus. The two bus
lines, SDA and SCL, must be high when the bus is not in
use. External pull-up resistors or current sources, such as
the LTC1694 SMBus accelerator, are required on these
lines. If the SDA and SCL pull-ups are absent, not con-
nected to the same positive supply as the LTC4259A’s V
DD
pin, or are not activated when the power is applied to the
LTC4259A, it is possible for the LTC4259A to see a START
condition on the I
2
C bus. The interrupt pin (INT) is only
updated between I
2
C transactions. Therefore if the
LTC4259A sees a START condition when it powers up
because the SCL and SDA lines were left floating, it will not
assert an interrupt (pull INT low) until it sees a STOP
condition on the bus. In a typical application the I
2
C bus
will immediately have traffic and the LTC4259A will see a
STOP so soon after power up that this momentary condi-
tion will go unnoticed.
Isolating the Serial Digital Interface
IEEE 802.3af requires that network segments be electri-
cally isolated from the chassis ground of each network
interface device. However, the network segments are not
required to be isolated from each other provided that the
segments are connected to devices residing within a
single building on a single power distribution system.
For simple devices such as small powered Ethernet
switches, the requirement can be met by using an iso-
lated power supply to power the entire device. This
implementation can only be used if the device has no
electrically conducting ports other than twisted-pair Eth-
ernet. In this case, the SDAIN and SDAOUT pins of the
LTC4259A can be connected together to act as a standard
I
2
C/SMBus SDA pin.
If the device is part of a larger system, contains serial
ports, or must be referenced to protective ground for
some other reason, the Power over Ethernet subsystem
including the LTC4259As must be electrically isolated
from the rest of the system. The LTC4259A includes
separate pins (SDAIN and SDAOUT) for the input and
output functions of the bidirectional data line. This eases
the use of optocouplers to isolate the data path between
the LTC4259As and the system controller. Figure 18
shows one possible implementation of an isolated inter-
face. The SDAOUT pin of the LTC4259A is designed to
drive the inputs of an optocoupler directly, but a standard
I
2
C device typically cannot. U1 is used to buffer I
2
C
signals into the optocouplers from the system controller
side. Schmitt triggers must be used to prevent extra
edges on transitions of SDA and SCL.
Bus Addresses and Protocols
The LTC4259A is a read-write slave device. The master
can communicate with the LTC4259A using the Write
Byte, Read Byte and Receive Byte protocols. The
LTC4259A’s primary serial bus address is
(010A
3
A
2
A
1
A
0
)b, as designated by pins AD3-AD0. All
LTC4259As also respond to the address (0110000)b,
allowing the host to write the same command into all of
the LTC4259As on a bus in a single transaction. If the
LTC4259A is asserting (pulling low) the INT pin, it will
also acknowledge the Alert Response Address (0001100)b
using the receive byte protocol.
The START and STOP Conditions
When the bus is idle, both SCL and SDA must be high. A
bus master (typically the host controller) signals the
beginning of communication with a slave device (like the
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