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參數(shù)資料
| 型號： | LTC4259ACGW#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/32頁 |
| 文件大小： | 0K |
| 描述： | IC CTRLR POE QUAD AC DISC 36SSOP |
| 產(chǎn)品培訓模塊： | Power over Ethernet |
| 標準包裝： | 32 |
| 控制器類型： | 以太網(wǎng)供電控制器（POE） |
| 接口： | I²C |
| 電源電壓： | 3 V ~ 4 V |
| 電流 - 電源： | 2.5mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-BSOP（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 36-SSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1338 (CN2011-ZH PDF) |
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LTC4259A
12
4259afb
disconnect enabled independently of the state of the Osc
Fail bit. See AC Disconnect under Applications Information
for more details. Bit 4 indicates that VEE has dropped be-
low the VEE UVLO level (typically –28V). Bit 5 signals that
the VDD supply has dropped below the VDD UVLO thresh-
old. Bit 7 indicates that the LTC4259A die temperature has
exceeded its thermal shutdown limit (see Note 5 under
Electrical Characteristics). The logical OR of bits 1, 4, 5 and
7 appears in the Interrupt register as the Supply Fault bit.
See the Misc Config register for information on masking the
Osc Fail bit out of the Supply Fault interrupt. The remaining
bits in the register are reserved and will always read as 0.
The Supply Event bits latch high and will remain high until
cleared by reading from address 0Bh.
Supply Event CoR (Address 0Bh): Supply Event Register,
Clear on Read. Read this address to clear the Fault Event
register. Address 0Bh returns the same data as address 0Ah,
and reading address 0Bh clears all bits at both addresses.
Status Registers
Port 1 Status (Address 0Ch): Port 1 Status Register, Read
Only. This register reports the most recent detection and
classification results for port 1. Bits 0-2 report the status
of the most recent detection attempt at the port and bits 4-6
report the status of the most recent classification attempt
at the port. If power is on, these bits report the detection/
classification status present just before power was turned
on. If power is turned off at the port for any reason, all bits
in this register will be cleared. See Table 1 for detection and
classification status bit encoding.
Port 2 Status (Address 0Dh): Port 2 Status Register, Read
Only. See Port 1 Status.
Port 3 Status (Address 0Eh): Port 3 Status Register, Read
Only. See Port 1 Status.
Port 4 Status (Address 0Fh): Port 4 Status Register, Read
Only. See Port 1 Status.
Power Status (Address 10h): Power Status Register, Read
Only. The lower four bits in this register report the switch
on/off state for the corresponding ports. The upper four
bits (the power good bits) indicate that the drop across the
power switch and sense resistor for the corresponding ports
is less than 2V (typ) and power start-up is complete. The
power good bits are latched high and are only cleared when
a port is turned off or the LTC4259A is reset.
Pin Status (Address 11h): External Pin Status, Read Only.
This register reports the real time status of the AUTO
(Pin 35) and AD0-AD3 (Pins 7-10) digital input pins. The
logic state of the AUTO pin appears at bit 0 and the AD0-AD3
pins at bits 2-5. The remaining bits are reserved and will
read as 0. AUTO affects the initial states of some of the
LTC4259A configuration registers at start-up but has no
effect after start-up and can be used as a general purpose
input if desired, as long as it is guaranteed to be in the
appropriate state at start-up.
Configuration Registers
Operating Mode (Address 12h): Operating Mode Configu-
ration, Read/Write. This register contains the mode bits for
each of the four ports in the LTC4259A. See Table 1 for mode
bit encoding. At power-up, all bits in this register will be set
to the logic state of the AUTO pin (Pin 35). See Operating
Modes in the Applications Information section.
Disconnect Enable (Address 13h): Disconnect Enable
Register, Read/Write. The lower four bits of this register
enable or disable DC disconnect detection circuitry at the
corresponding port. If the DC Discon Enable bit is set the
port circuitry will turn off power if the current draw at the
port falls below IMINformorethantDIS.IMINisequaltoVMIN/
RS, where RS is the sense resistor and should be 0.5 for
IEEE 802.3af compliance. If the bit is clear the port will not
remove power due to low current.
The upper four bits enable or disable AC disconnect on the
corresponding port. When a port’s AC disconnect bit is set,
the LTC4259A senses the impedance of that port by forc-
ing an AC voltage on the port’s DETECT pin and measuring
the AC current. If the DETECT pin sinks less than IACDMIN
for more than tDIS, the port will turn off power. If the bit is
clear, the port will not remove power due to high port
impedance (AC current below IACDMIN).
The DC and AC disconnect signals that reset tDIS are ORed
together and either sensing method (if they are both en-
abled) will keep the port powered. A port with neither DC
or AC disconnect enabled will not power off automatically
when the PD is removed.
REGISTER FU CTIO S
U
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