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參數(shù)資料
| 型號(hào)： | LTC4252-1CMS8 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | TRANS ARRAY NPN/NPN SSMINI-6 |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | PLASTIC, MSOP-8 |
| 文件頁數(shù)： | 22/32頁 |
| 文件大小： | 327K |
| 代理商： | LTC4252-1CMS8 |
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LTC4252-1/LTC4252-2
22
425212f
Figure 10. Undervoltage Timing (All Waveforms are Referenced to V
EE
)
UV
TIMER
GATE
SENSE
SS
DRAIN
PWRGD
5.8
μ
A
58
μ
A
5.8
μ
A
5.8
μ
A
58
μ
A
UV DROPS BELOW V
UVLO
. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES
UV CLEARS V
UVHI
, CHECK OV CONDITION, GATE < V
GATEL
, SENSE < V
CB
, SS < 20 V
OS
AND TIMER < V
TMRL
1
2
3 4 56
7
8 9
TIMER CLEARS V
TMRL
, CHECK GATE < V
GATEL
, SENSE < V
CB
AND SS < 20 V
OS
1011
4252-1/2 F10
V
ACL
V
CB
230
μ
A + 8 I
DRN
20 V
OS
V
IN
– V
GATEH
V
DRNL
V
DRNCL
20 (V
CB
+ V
OS
)
20 (V
ACL
+ V
OS
)
V
GATEL
V
TMRL
V
TMRH
V
UVHI
V
UVLO
GATE
START-UP
INITIAL TIMING
APPLICATIU
activates. The TIMER capacitor, C
T
, is charged by a (230
μ
A
+ 8 I
DRN
) current pull-up. As the load capacitor nears full
charge, load current begins to decline. At point 8, the load
current falls and the SENSE voltage drops below V
ACL
(t).
The analog current limit loop shuts off and the GATE pin
ramps further. At time point 9, the SENSE voltage drops
below V
CB
and the fault TIMER cycle ends, followed by a
5.8
μ
A discharge cycle (cool off). When GATE ramps past
V
GATEH
threshold at time point 10, PWRGD pulls low. At
time point 11, GATE reaches its maximum voltage as
determined by V
IN
.
W
U
U
Undervoltage Timing
In Figure 10 when UV pin drops below V
UVLO
(time
point1), the LTC4252 shuts down with TIMER, SS and
GATE all pulling low. If current has been flowing, the
SENSE pin voltage decreases to zero as GATE collapses.
When UV recovers and clears V
UVHI
(time point 2), an
initial timer cycle begins followed by a start-up cycle.
V
IN
Undervoltage Lockout Timing
The V
IN
undervoltage lockout comparator, UVLO, has a
similar timing behavior as the UV pin timing except it looks
for V
IN
< (V
LKO
– V
LKH
) to shut down and V
IN
> V
LKO
to
start. In an undervoltage lockout condition, both UV and
OV comparators are held off. When V
IN
exits undervoltage
lockout, the UV and OV comparators are enabled.
Undervoltage Timing with Overvoltage Glitch
In Figure 11, both UV and OV pins are connected together.
When UV clears V
UVHI
(time point 1), an initial timing cycle
starts. If the system bus voltage overshoots V
OVHI
as
shown at time point 2, TIMER discharges. At time point 3,
the supply voltage recovers and drops below the V
OVLO
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| LTC4252-1CMS8#PBF | 功能描述:IC CNTRLR HOTSWAP NEGVOLT 8-MSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 熱交換 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 類型:熱交換控制器 應(yīng)用:-48V 遠(yuǎn)程電力系統(tǒng)，AdvancedTCA ? 系統(tǒng)，高可用性 內(nèi)部開關(guān):無 電流限制:可調(diào) 電源電壓:11.5 V ~ 14.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:10-TFSOP，10-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:10-MSOP 包裝:管件 |
| LTC4252-1CMS8#TR | 功能描述:IC CNTRLR HOTSWAP NEGVOLT 8-MSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 熱交換 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 類型:熱交換控制器 應(yīng)用:-48V 遠(yuǎn)程電力系統(tǒng)，AdvancedTCA ? 系統(tǒng)，高可用性 內(nèi)部開關(guān):無 電流限制:可調(diào) 電源電壓:11.5 V ~ 14.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:10-TFSOP，10-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:10-MSOP 包裝:管件 |
| LTC4252-1CMS8#TRPBF | 功能描述:IC CNTRLR HOTSWAP NEGVOLT 8-MSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 熱交換 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 類型:熱交換控制器 應(yīng)用:-48V 遠(yuǎn)程電力系統(tǒng)，AdvancedTCA ? 系統(tǒng)，高可用性 內(nèi)部開關(guān):無 電流限制:可調(diào) 電源電壓:11.5 V ~ 14.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:10-TFSOP，10-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:10-MSOP 包裝:管件 |
| LTC4252-1CMS8PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Negative Voltage Hot Swap Controllers |
| LTC4252-1CMS8TR | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Negative Voltage Hot Swap Controllers |
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