參數(shù)資料
型號(hào)： LTC4241IGN#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 13/16頁(yè)
文件大小： 279K
描述： IC CTRLR HOTSWAP 3.3V AUX 20SSOP
標(biāo)準(zhǔn)包裝： 55
類(lèi)型： 熱交換控制器
應(yīng)用： PCI，PCI-X
內(nèi)部開(kāi)關(guān)： 無(wú)
電源電壓： 3.3V，5V，±12V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 20-SSOP
包裝： 管件
LTC4241
13
sn4241 4241f
The current limit and the foldback current level (at the
V
OUT
 = 0V) are given by:
I
LIMIT
 = 55mV/R
SENSE
I
FOLDBACK
 = 9mV/R
SENSE
As a design aid, the current limit and foldback level for
commonly used values for R
SENSE
 are given in Table 2.
Table 2. I
LIMIT
 and I
FOLDBACK
 vs R
SENSE
R
SENSE
 (&)
I
LIMIT
I
FOLDBACK
0.005
11A
1.8A
0.006
9.2A
1.5A
0.007
7.9A
1.3A
0.008
6.9A
1.1A
0.009
6.1A
1.0A
0.01
5.5A
0.9A
The current limit for the internal 12V switch is set at
850mA folding back to 300mA and the 12V switch at
450mA folding back to 200mA.
In systems where it is possible to exceed the current limit
for a short amount of time, it might be necessary to
prevent the analog current loop from responding quickly
so the output voltage does not droop. This can be accom-
plished by adding an RC filter across the sense resistor as
shown in Figure 6. R
F
 should be 20& or less to prevent
offset errors. A capacitor, C
F
, of 0.1礔 gives a delay of
about 1.5祍 and a 1礔 capacitor gives a delay of about
15祍.
power path (Figure 1). The resistor R3 provides load
current fault detection and R6 prevents high frequency
oscillation in Q3.
When power is first applied to V
AUXIN
, the AUXGATE pin
pulls low. A low-to-high transition at the AUXON pin
initiates the AUXGATE ramp up (Figure 7). The AUXGATE
is pulled high by an internal 10礎(chǔ) current source and the
pass transistor is allowed to turn on. As the auxiliary
controller does not have the foldback current limit feature
and timer control, the inrush supply current during power-
up is limited by ramping the gate of the pass transistor at
a controlled rate (dV/dt = 10礎(chǔ)/C3) where C3 is the total
external capacitance between AUXGATE and ground.
With proper selection of the C3 capacitance value, the
inrush current (I = C
LOAD
" dV/dt = 10礎(chǔ) " C
LOAD
/C3) is
limited to a value less than the current limit set by the sense
resistor R3. This prevents the circuit breaker from tripping
during power-up. C
LOAD
 is the total load capacitance on
the 3.3V auxiliary supply line. For example, for C3 = 10nF,
C
LOAD
 = 470礔, R3 = 0.07&, I
LIMIT
 = 0.7A, the inrush
current will be 0.47A < I
LIMIT
. The ramp-up time for
3.3V
AUX
  output to reach its final value is equal to
t = (V
AUXIN
" C3)/10礎(chǔ).
A high-to-low transition at the AUXON pin initiates a
AUXGATE ramp-down at a slope of 200礎(chǔ)/C3 as the
AUXGATE is pulled to ground by an internal 200礎(chǔ) current
source. This will allow the load capacitance on the supply
line to discharge while the AUXGATE pulls low to turn off
the external N-channel pass transistor.
APPLICATIO S I FOR ATIO
U
U
U
Figure 6. Delay in the Current Limit Loop
4
3
2
1
5V
IN
R1
0.007&
R4
10&
R7
100&
R
F
20&
Q1
IRF7413
5V
OUT
5A
C
F
1礔
C1
0.047礔
17
16
15    18
*ADDITIONAL PINS
OMITTED FOR
CLARITY
LTC4241*
5V
IN
5V
SENSE
GATE 5V
OUT
Figure 7. Power-Up/Down Sequence for 3.3V Auxiliary Supply
Power-Up/Down Sequence for 3.3V Auxiliary Supply
external N-channel pass transistor Q3 in the 3.3V
AUX
AUXON
2V/DIV
AUXGATE
5V/DIV
3.3V
AUX
2V/DIV
5ms/DIV
4241 F07
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