參數(shù)資料
型號(hào): LTC4230CGN#TRPBF
廠商: Linear Technology
文件頁數(shù): 17/36頁
文件大?。?/td> 384K
描述: IC CONTRLLR HOT SWAP TRPL 20SSOP
標(biāo)準(zhǔn)包裝: 2,500
類型: 熱交換控制器
應(yīng)用: 通用
內(nèi)部開關(guān):
電源電壓: 1.7 V ~ 16.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 20-SSOP
包裝: 帶卷 (TR)
17
LTC4230
 4230f
reduces, and the internal servo loop disengages. At the
end of the soft-start cycle (Time Point 8), all RESETn are
high and all SLOW COMPn are armed.
Power-Off Cycle
As shown at Time Point 9, an external hard reset is initiated
by pulling the ON pin low (V
ON
 < 1.234V). All GATEn pin
voltages are ramped to ground by the internal 200礎(chǔ)
current sources, discharging C
GATEn
 and turning off the
pass transistors. As C
LOADn
 discharges, the output voltage
crosses FBCOMPns threshold, signaling a power bad
condition at Time Point 10. RESETn then asserts low.
1
3
7
6
5
8
4
FIRST TIMING CYCLE
20礎(chǔ) PULL-UP
20礎(chǔ) PULL-UP
LOAD CURRENT IS REGULATING AT 50mV/R
SENSEn
4230 F06
NORMAL MODE
SECOND TIMING
CYCLE
CHECK FOR FILTER LOW (< V
REF
)
CHECK FOR FAULT HIGH (> V
REF
 + 50mV)
2
CHECK FOR GATEn < 0.25V
FAST COMPARATOR
ARMED
IF ON IS LOW AND
V
FBn
 < 1.234V,
RESET 1, RESET 2 and RESET 3
PULL LOW, RESPECTIVELY
ON
TIMER
GATEn
V
OUTn
I
LOADn
GATEn
V
OUTn
RESET 1
RESET 2,
RESET 3
10礎(chǔ) PULL-UP
200礎(chǔ) PULL-DOWN
SLOW COMPARATOR ARMED
9
10
POWER GOOD
(V
FBn
 > 1.237V)
POWER BAD
(V
FBn
 < 1.234V)
200礎(chǔ) PULL-DOWN
Figure 6. Normal Power-Up Sequence (with Current Limiting in Second Timing Cycle)
FREQUENCY COMPENSATION AT SOFT-START
If the external gate input capacitance (C
ISS
) is greater than
600pF, no external gate capacitor is required at GATEn to
stabilize the internal current-limiting loop during soft-
start. Otherwise, connect an external gate capacitor be-
tween the GATEn and GND pins to increase the total gate
capacitance above 600pF. The servo loop that controls the
external MOSFET during current limiting has a unity-gain
frequency of about 105kHz and phase margin of 80?for
external MOSFET gate input capacitances to 2.5nF.
APPLICATIO  S I FOR  ATIO
U
U
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