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參數(shù)資料
| 型號(hào)： | LTC4212IMS#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 13/24頁 |
| 文件大小： | 234K |
| 描述： | IC CTRLR HOTSWAP TIMEOUT 10MSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 2.5 V ~ 16.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
13
LTC4212
4212f
OPERATIO
V
GS
= 10V. From Equation 6, the slew rate is calculated to
be 3.03V/ms.
The inrush current being delivered to the load while the
GATE pin is ramping depends on C
LOAD
and C
GATE
. The
external N-channel MOSFET acts as a source follower so
that its source (load) voltage ramps up at the same rate as
the GATE pin. The output current component for capacitor
charging is given by Equation 7:
I
INRUSH
= C
LOAD
" dV
GATE
/dt
(7)
=10礎(chǔ) " C
LOAD
/C
GATE
where, C
LOAD
is the total capacitance at the load side of the
MOSFET. For example, if C
GATE
= 3300pF and
C
LOAD
= 2000礔, the inrush current charging C
LOAD
is
6.06A. Note that the soft-start circuit will servo the inrush
to I
LIMIT(SOFTSTART)
or 5A in this example and dV
GATE
/dt
will be lower than calculated from Equation 6.
Frequency Compensation at Soft-Start
If the external MOSFETs gate input capacitance (C
ISS
) is
greater than 600pF, no external gate capacitor is required
at GATE to stabilize the internal current-limiting loop
during soft-start. Otherwise, connect a gate capacitor
between the GATE pin and ground to increase the total gate
capacitance to be equal to or above 600pF. The servo loop
that controls the external MOSFET during current limiting
has a unity-gain frequency of about 105kHz and phase
margin of 80?for external MOSFET gate input capaci-
tances of up to 2.5nF.
Electronic Circuit Breaker
The LTC4212 features an electronic circuit breaker func-
tion that protects against supply overvoltage, externally-
generated fault conditions, shorts or excessive load current
conditions and power good faults. If the circuit breaker
trips, the GATE pin is immediately pulled to ground, the
external N-channel MOSFET is quickly turned OFF and
FAULT is latched low.
The circuit breaker trips whenever the voltage across the
sense resistor exceeds two different levels, set by the
LTC4212s SLOW COMP and FAST COMP thresholds (see
Block Diagram). The SLOW COMP trips the circuit breaker
if the voltage across the SENSE resistor (V
CC
V
SENSE
=
V
CB
) is greater than 50mV for 18祍. The FAST COMP trips
the circuit breaker to protect against fast load overcurrents
if the transient voltage across the sense resistor is greater
than 150mV for 500ns.
The timing diagram of Figure 2 illustrates when the
LTC4212s electronic circuit breaker is armed. After the
first timing cycle, the LTC4212s FAST COMP is armed at
Time Point 6. This ensures that the system is protected
against a short-circuit condition during the second timing
cycle after C
LOAD
has been fully charged. At Time Point 8,
SLOW COMP is armed when the internal control loop is
disengaged.
The timing diagram in Figure 4 illustrates the operation of
the LTC4212 when the load current conditions exceed the
threshold of SLOW COMP (V
CB(SLOW)
> 50mV).
Circuit Breaker Reset
Referring to the Block Diagram, the ON pin drives two
internal comparators, COMP1 and COMP2. COMP1 is
referenced to 1.236V and has a hysterisis of 80mV.
COMP2 is referenced to 0.5V and has a hysterisis of 45mV.
The outputs of the two comparators drive an internal flip-
flop to generate a typical high and low ON pin threshold of
1.31V and 0.455V respectively.
If the voltage at the ON pin is driven below 0.455V for more
than 10祍, all internal control logic except the circuit
breaker is reset. A 200礎(chǔ) pull-down current source is
connected to the GATE pin to pull it down gradually.
Holding the ON pin below 0.455V for 120祍 or longer,
resets the circuit breaker. Following reset, the ON pin must
be taken above 1.316V to start a power-up sequence.
Normal Operating Sequence
Figure 2 illustrates the normal power-up sequence for two
different applications. The PGI (RST) and PGF (RST)
waveforms are valid for applications which use the PGI pin
to monitor the RST output of a supply monitor IC. The PGI
(PGOOD) and PGF (PGOOD) waveforms refer to applica-
tions that tie the PGI pin to the PGOOD output
of a DC/DC converter. All other waveforms in Figure 2
are common to both applications. The PGI and PGF
waveforms for applications that connect PGI pin to the
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