參數(shù)資料
型號: LTC4210-2CS6#TRM
廠商: Linear Technology
文件頁數(shù): 11/20頁
文件大?。?/td> 251K
描述: IC CONTROLLER HOT SWAP TSOT23-6
標準包裝: 1
類型: 熱交換控制器
應用: 通用
內(nèi)部開關:
電源電壓: 2.7 V ~ 16.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-6 細型,TSOT-23-6
供應商設備封裝: SOT-23-6
包裝: 剪切帶 (CT)
產(chǎn)品目錄頁面: 1342 (CN2011-ZH PDF)
其它名稱: LTC4210-2CS6
LTC4210-2CS6#TRMCT
LTC4210-2CS6-ND
11
LTC4210-1/LTC4210-2
 421012f
Whichever method of compensation is used, board level
short-circuit testing is highly recommended as board
layout can affect transient performance. Beside frequency
compensation, the total gate capacitance C
GATE
  also
determines the GATE start-up as in Equation 6. The C
GATE
should be kept below 0.15礔 at high supply operation as
the capacitive energy ( 0.5 " C
GATE
 " V
GATE
2
 ) is discharged
by the LTC4210 internal pull-down transistor. This pre-
vents the internal pull-down transistor from overheating
when the GATE turns off and/or is servoing during current
limiting.
Timer Function
The TIMER pin handles several key functions with an
external capacitor, C
TIMER
. There are two comparator
thresholds: COMP1 (0.2V) and COMP2 (1.3V). The four
timing current sources are:
5礎 pull-up
60礎 pull-up
2礎 pull-down
100礎 pull-down
The 100礎 is a nonideal current source approximating a
7k resistor below 0.4V.
Initial Timing Cycle
When the card is being inserted into the bus connector, the
long pins mate first which brings up the supply V
IN
 at time
point 1 of Figure 3. The LTC4210 is in reset mode as the
ON pin is low. GATE is pulled low and the TIMER pin is
pulled low with a 100礎 source. At time point 2, the short
pin makes contact and ON is pulled high. At this instant, a
start-up check requires that the supply voltage be above
UVLO, the ON pin be above 1.3V and the TIMER pin voltage
be less than 0.2V. When these three conditions are ful-
filled, the initial cycle begins and the TIMER pin is pulled
high with 5礎. At time point 3, the TIMER reaches the
COMP2 threshold and the first portion of the initial cycle
ends. The 100礎 current source then pulls down the
TIMER pin until it reaches 0.2V at time point 4. The initial
cycle delay (time point 2 to time point 4) is related to
C
TIMER
 by equation:
t
INITIAL
 H 272.9 " C
TIMER
 ms/礔
(5)
When the initial cycle terminates, a start-up cycle is
activated and the GATE pin ramps high. The TIMER pin
continues to be pulled down towards ground.
APPLICATIO S I FOR ATIO
U
U
U
1
>2.5V
COMP2
100礎
10礎
V
IN
V
ON
V
GATE
RESET
MODE
V
OUT
V
TIMER
2
3 4 5
6
7
COMP1
4210 F03
5礎
INITIAL
CYCLE
START-UP
CYCLE
NORMAL
CYCLE
DISCHARGE
BY LOAD
V
TH
>1.3V
Figure 3. Normal Operating Sequence
Start-Up Cycle Without Current Limit
The GATE is released with a 10礎 pull-up at time point 4
of Figure 3. At time point 5, GATE reaches the external
MOSFET threshold V
TH
 and V
OUT
 starts to follow the GATE
ramp up. If the R
SENSE
 current is below the current limit,
the GATE ramps at a constant rate of:


=
V
T
I
C
GATE
GATE
GATE
(6)
where C
GATE
 is the total capacitance at the GATE pin.
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