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參數(shù)資料
| 型號： | LTC3851AIUD-1#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.05 A SWITCHING CONTROLLER, 810 kHz SWITCHING FREQ-MAX, PQCC16 |
| 封裝： | 3 X 3 MM, LEAD FREE, PLASTIC, MO-220WEED-2, QFN-16 |
| 文件頁數(shù)： | 13/30頁 |
| 文件大?。?/td> | 0K |
| 代理商： | LTC3851AIUD-1#TRPBF |
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LTC3851A-1
20
3851a1fa
applicaTions inForMaTion
Fault Conditions: Current Limit and Current Foldback
The LTC3851A-1 includes current foldback to help limit
load current when the output is shorted to ground. If the
output falls below 40% of its nominal output level, the
maximum sense voltage is progressively lowered from
its maximum programmed value to about 25% of the
that value. Foldback current limiting is disabled during
soft-start or tracking. Under short-circuit conditions
with very low duty cycles, the LTC3851A-1 will begin
cycle skipping in order to limit the short-circuit current.
In this situation the bottom MOSFET will be dissipating
most of the power but less than in normal operation. The
short-circuit ripple current is determined by the minimum
on-time, tON(MIN), of the LTC3851A-1 (≈90ns), the input
voltage and inductor value:
IL(SC) = tON(MIN)
VIN
L
The resulting short-circuit current is:
ISC =
1/4MaxVSENSE
RSENSE
– 1
2
IL(SC)
Programming Switching Frequency
TosettheswitchingfrequencyoftheLTC3851A-1,connect
a resistor, RFREQ, between FREQ/PLLFLTR and GND. The
relationship between the oscillator frequency and RFREQ
is shown in Figure 7. A 0.1F bypass capacitor should be
connected in parallel with RFREQ.
Phase-Locked Loop and Frequency Synchronization
TheLTC3851A-1hasaphase-lockedloop(PLL)comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the top MOSFET
to be locked to the rising edge of an external clock signal
applied to the MODE/PLLIN pin. This phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the FREQ/PLLFLTR pin. Note
that the LTC3851A-1 can only be synchronized to an
external clock whose frequency is within range of the
LTC3851A-1’s internal VCO.This is guaranteed to be be-
tween 250kHz and 750kHz. A simplified block diagram is
shown in Figure 8.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sunk con-
tinuouslyfromthephasedetectoroutput,pullingdownthe
FREQ/PLLFLTR pin. When the external clock frequency is
less than fOSC, current is sourced continuously, pulling up
theFREQ/PLLFLTRpin.Iftheexternalandinternalfrequen-
ciesarethesamebutexhibitaphasedifference,thecurrent
sourcesturnonforanamountoftimecorrespondingtothe
phase difference. The voltage on the FREQ/PLLFLTR pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor CLP holds the voltage.
Figure 7. Relationship Between Oscillator Frequency
and Resistor Connected Between FREQ/PLLFLTR and GND
Figure 8. Phase-Locked Loop Block Diagram
RFREQ (k)
20
250
OSCILLATOR
FREQUENCY
(kHz)
300
400
450
500
750
600
60
100
120
3851A1 F07
350
650
700
550
40
80
140 160
DIGITAL
PHASE/
FREQUENCY
DETECTOR
VCO
2.7V
RLP
CLP
3851A1 F08
FREQ/PLLFLTR
EXTERNAL
OSCILLATOR
MODE/
PLLIN
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